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superconductor-electronics

Here are 7 public repositories matching this topic...

Single-Flux-Quantum / qSVS

[IEEE TASC] qSVS: Superconducting Circuit Verification System and formal equivalence checking framework.

reproducible-research eda spice verilog josim josephson-junctions rsfq cryogenic-computing superconducting-circuits single-flux-quantum superconductor-electronics ieee-tasc

Updated Oct 6, 2026
SystemVerilog

Single-Flux-Quantum / JoSIM

[IEEE TASC] JoSIM: High-performance SPICE-level superconductor circuit simulator for Single-Flux-Quantum logic.

reproducible-research eda spice verilog josim josephson-junctions rsfq cryogenic-computing superconducting-circuits single-flux-quantum superconductor-electronics ieee-tasc

Updated Oct 6, 2026
C++

Single-Flux-Quantum / sfq-learn-public

Open-source tutorials, interactive notebooks, and guides for Single-Flux-Quantum circuit engineering.

reproducible-research eda spice verilog josim josephson-junctions rsfq cryogenic-computing superconducting-circuits single-flux-quantum superconductor-electronics ieee-tasc

Updated Oct 6, 2026
JavaScript

Single-Flux-Quantum / .github

Community health files and default organization profiles for Single-Flux-Quantum.

reproducible-research eda spice verilog josim josephson-junctions rsfq cryogenic-computing superconducting-circuits single-flux-quantum superconductor-electronics ieee-tasc

Updated Oct 11, 2026

Single-Flux-Quantum / design-and-verification-of-sfq-cell-library-for-superconducting-lsi-digital-circuits

[IEEE TASC 2021] Design and Verification of SFQ Cell Library for Superconducting LSI Digital Circuits

reproducible-research spice verilog dff cell-library rsfq standard-cell-library cryogenic-computing superconducting-circuits superconductor-electronics triple-engine simit-nb03 pscan2 lsi-circuits operating-margins flux-trapping moat-design rdff

Updated Oct 15, 2026
Python

Single-Flux-Quantum / conversion-method-of-netlists-consisting-of-conventional-logic-gates-to-rsfq-circuits

[IEEE TASC 2020] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

reproducible-research eda spice verilog sat-solver logic-synthesis atpg integer-linear-programming rsfq standard-cell iscas85 superconducting-circuits superconductor-electronics triple-engine path-balancing confluence-buffer resettable-dff nimply-gate

Updated Oct 15, 2026
Python

Single-Flux-Quantum / design-of-64-bit-alu-using-improved-timing-characterization-for-rsfq-cell-library

[IEEE TASC 2021] Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

reproducible-research spice verilog alu static-timing-analysis arithmetic-logic-unit rsfq kogge-stone superconducting-circuits sfq5ee superconductor-electronics triple-engine 64-bit-alu timing-characterization liberty-file timing-back-annotation process-corners hypres

Updated Oct 15, 2026
Python

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