standard-cell

Here are 8 public repositories matching this topic...

furrtek / SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

asic fpga arcade-game video-game reverse-engineering arcade verilog chip konami hdl silicon cpld repro taito decap gate-array standard-cell

Updated Sep 28, 2026
Verilog

furrtek / ASICRE

Star

Logic cell info for gate array and standard cell ASIC reverse-engineering

asic electronics reverse-engineering chip silicon gate-array standard-cell

Updated Jul 2, 2020

Single-Flux-Quantum / conversion-method-of-netlists-consisting-of-conventional-logic-gates-to-rsfq-circuits

Star

[IEEE TASC 2020] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

reproducible-research eda spice verilog sat-solver logic-synthesis atpg integer-linear-programming rsfq standard-cell iscas85 superconducting-circuits superconductor-electronics triple-engine path-balancing confluence-buffer resettable-dff nimply-gate

Updated Oct 15, 2026
Python

rodrigowue / pyLEX

Star

pyLEX - SPICE STD-CELL ARCS EXTRACTOR (but in Python)

asic eda spice microelectronics boolean-logic standard-cell

Updated Feb 3, 2025
Python

rodrigowue / SCLF

Star

A program that allows the filtering of standard cell libraries by the transistor stack

eda vlsi genus microelectronics standard-cell standard-cell-library

Updated Jan 20, 2025
C++

Mysha-Fathima / PHYSICAL--DESIGN-SKY130-OpenLane-Workshop

Star

10 Days Workshop of Digital VLSI SoC Physical Design Program from 6weeks+10 days of VSDSQUADRON RTL-GDSII course

linux-desktop routing-algorithm vlsi-physical-design power-distribution-system timing-analysis github-actions floorplanning standard-cell sky130 github-cloning rtl-to-gdsii tritonroute asic-backend library-binding cmos-layout

Updated Oct 7, 2026
Verilog

vyges-tools / tap

Star

Row cutting and physical-cell insertion over the OpenDB design database: tap cells, endcaps, corners

rust asic eda opendb physical-design openroad standard-cell open-source-silicon tapcell endcap

Updated Oct 16, 2026
Rust

Shreyasimum / custom-full-adder-rtl2gds

Star

End-to-end Digital VLSI project demonstrating a Full Adder from RTL to GDS using Yosys and OpenROAD, extended with a custom CMOS Full Adder standard cell and system-level evaluation.

asic vlsi yosys cmos digital-design physical-design openroad standard-cell sky130 rtl-to-gds

Updated Jan 6, 2026
Verilog

Add this topic to your repo

To associate your repository with the standard-cell topic, visit your repo's landing page and select "manage topics."

Learn more