[IEEE TASC 2020] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates
reproducible-research eda spice verilog sat-solver logic-synthesis atpg integer-linear-programming rsfq standard-cell iscas85 superconducting-circuits superconductor-electronics triple-engine path-balancing confluence-buffer resettable-dff nimply-gate
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Updated
Oct 15, 2026 - Python