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Changes requested — not ready for Class-A qualification [P1] Correct the MP2307 output voltage. R2 = 10 kΩ and R3 = 3.16 kΩ produce approximately 3.85 V from the MP2307’s 0.925 V feedback reference, not the documented 5 V. Correct the divider and verify the rail under load against the MP2307 datasheet. [P1] Correct Q1 gate protection. D1 is connected between the MOSFET gate and ground, not source and gate, so it does not clamp VGS. The source is on the 12 V input while the gate is pulled toward ground; verify the Si2301 maximum VGS and implement a correctly rated source-gate clamp. The source also uses [P1] Use a real, matching TVS part. D2 uses registry part [P1] Apply power geometry. The board claims 1.5 A input and 800 mA on the 5 V rails, but no power netclasses are applied, so critical paths may use the default 0.127 mm width. Apply suitable current-carrying widths and clearances, then rerun routing, DRC, and thermal checks. [P1] Remove the via-in-pad failure. The current board is explicitly [P2] Complete qualification evidence. Twenty parts lack distributor identity, several protection parts still use placeholder operating envelopes, and there are no fabrication artifacts, independent sign-off, thermal measurements, conducted-emissions results, or load-step measurements. The schematic also retains ground-flag and distant-decoupling readability findings. Resolve these before accepting this as Class-A qualification material. |
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JeffMboya
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@SammyOina The board is now agent-made: 34/34 nets, DRC 0 errors. Three-export hashes and the parts split follow; the 0.6/0.3 mm vias are in Limitations. |
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Changes requested
[P1] Do not present this as Class-A qualification evidence yet
Issue #39 requires a complete, reproducible qualification package: Gerbers, drill files, pick-and-place data, STEP, DRC/ERC results, BOM, and independent PCB review. This PR explicitly describes the board as a draft and does not provide the complete manufacturing artifacts or independent sign-off. Please add the final exported artifacts and a reproducible report generated from the reviewed commit before treating this as Class-A qualification evidence.
[P1] Resolve the declared-versus-exported power geometry
The source declares substantially larger power traces and vias than the exported/report data uses, including 0.8/1.0 mm power widths and 0.8/0.4 mm vias versus reported 0.6/0.3 mm vias and narrowed power routes. A clean generic DRC does not prove that the product’s declared power constraints were honored. Make the router enforce these constraints, or explicitly revise and independently verify the electrical and thermal operating envelope; then regenerate and inspect the final exported board.
[P1] Verify and authenticate every critical power-path part
The verification report says the MP2307 exposed-pad footprint, TPS22918 pin map, inductor ratings, compensation network, and protection parts were authored or recalled from memory and remain unverified. For qualification, add manufacturer datasheet provenance, checked pin/land patterns, voltage/current/thermal margins, and independent reviewer sign-off for each critical part. Do not rely on a clean connectivity report when the physical package or electrical identity is still uncertain.
[P1] Close the input-transient and thermal risks
The current documentation does not define a verified surge envelope or prove that the input protection keeps the MP2307 within its operating limits. In particular, the SMAJ15A listing gives a 24.4 V maximum clamp while the MP2307 datasheet specifies 23 V recommended input operation; document the source impedance, surge case, clamp behavior, and downstream margin. Also resolve the AMS1117 thermal design: no required copper area or validated thermal result is given, while the design notes a 0.5 A target and up to roughly 0.66–0.94 W dissipation. Use a validated thermal design or encode and verify a lower product limit.
[P2] Fix the registry dependency and reconcile the qualification evidence
The branch still carries the d_schottky identity/footprint mismatch (a through-hole 1N5819/C8224 identity paired with a SOD-123 footprint); use the corrected registry entry or update this branch before qualification. Also reconcile the conflicting artifact totals, including the README’s 43 vias versus the verification report’s 32 vias and the differing segment/length totals. Regenerate all reports and artifacts from one final reviewed commit so the qualification evidence cannot describe different board revisions.
absmach#39's third test case is a protected power-entry board with reverse-polarity and over-current components. It gets its own pull request rather than sharing one with four other boards, so the power stage can be reviewed as a power stage. Two layers, no MCU, 23 components, 13 nets, 47.23 x 37.71 mm: 12 V in, a Si2301 P-FET for reverse polarity with a 12 V zener on its gate, a 1.5 A polyfuse, an SMAJ15A TVS array, an MP2307 buck to 5 V, a TPS22918 soft-start load switch, and an AMS1117 3V3 rail for logic a carrier would add. The order of the chain is the claim being reviewed. The TVS sits after the fuse, because a TVS in front of the fuse has nothing to limit the fault current it conducts. U1's exposed pad is tied to GND: the part declares it `required`, so leaving it floating is an error rather than a silent thermal fault. Measured on this tree, not carried over: 13 of 13 nets closed, nothing open, 274.8 mm of copper over 101 segments and 17 vias, no track under the 0.127 mm floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a pad, and `kicad-cli pcb drc` reports nothing at all -- zero errors, zero warnings, zero unconnected pads, zero schematic-parity differences. It is the cleanest routed board in the Class-A set and the package validates as fabrication-ready. Both of this board's old blockers are gone. The 16 October re-measure reported 19 `annular_width` errors -- absmach#216, the net classes asking for a 0.6 mm via over a 0.4 mm drill that the declared process would not plate -- and the open switch node went with the routing those vias forced. What is left is in the README's Limitations. The one worth a reviewer's time is `W-SYNTH-THERMAL-001`: the AMS1117's junction is estimated at about 107 C, 1360 mW through a declared 60 C/W, which is the figure that decides whether that rail belongs on a linear regulator. Carved out of the five-board bundle in absmach#196.
It was a correct protection chain that nobody could bring up, integrate or
switch. 23 components to 42, and every addition answers something a reviewer
would have asked.
The one real electrical defect first. U1's COMP and SS pins were unconnected.
Both are declared `passive` so nothing complained, but COMP is the MP2307's
error-amplifier output: with no compensation network the loop has no dominant
pole, so the converter rings or refuses to regulate. R6 6.2k and C8 2.2nF to
ground, which is the datasheet's typical network for a 5 V output -- stated in
the source as typical rather than measured, because it is. C9 100nF on SS sets
the start ramp so the buck does not current-limit into its own output
capacitance.
Then the things that make it a module rather than a schematic:
- Four rails declared with `power`, so the regulator-range and load-budget
rules have something to check and the schematic names V12_PROT, V5, V5_SW
and V3V3 instead of numbering them.
- J2 is a 1x4 header, not a 1x3: switched 5 V, GND, enable, GND. A
downstream system can now shed the load the TPS22918 exists to switch, and
the enable sits between two grounds so a short to either neighbour turns
the output off rather than on.
- R7 on QOD discharges the output when the switch opens. Without it a
capacitive load holds the rail up after shutdown and the next soft-start
begins from an unknown voltage.
- D4 and R8 12k indicate the protected rail, behind the FET and the fuse, so
the indicator is dark on reverse polarity and dark on a tripped fuse --
the two faults a person needs to see. D3 on 3V3 stays.
- U3 is an LP5907, not an AMS1117. The housekeeping rail drives an indicator
and whatever logic a carrier adds, so it wants tens of milliamps, not 800,
and an AMS1117 declared at its full rating puts its own junction near
107 C through 60 C/W. W-SYNTH-THERMAL-001 is gone with it.
- C10 and C11 bypass the switch input and the output at the connector, which
is where a downstream load sees the impedance. Both E-SYNTH-POWER-004
findings cleared.
- Five test points, one per rail plus a ground reference, and four M2.5
mounting holes hinted to the corners with two fiducials.
- J1 on the left edge and J2 on the right: power in one side and out the
other, which is how a module gets wired into a system and what keeps both
connectors clear of the corner holes.
`synth validate` reports zero errors. E-SYNTH-POWER-001 twice,
E-SYNTH-POWER-006 and W-SYNTH-THERMAL-001 were all present before and are all
gone -- not suppressed, answered.
Measured on this tree:
18 of 18 nets closed, none open
582.3 mm over 179 segments and 32 vias
kicad-cli pcb drc: 0 errors, 0 unconnected, 0 warnings
routing verdict: validation_failed, not fabrication-ready
Not fabrication-ready, and for one reason: a single stitching via lands inside
U2.2, the load switch's ground pad, and this board declares the standard tier
which does not fill vias. Same net, so it shorts nothing -- it is the ground
pour reaching the bottom layer -- but an unfilled via in a pad wicks solder,
so refusing it is right. `requires via_in_pad` is deliberately not declared:
asking a two-layer power front end to be built on a filled-via process for one
ground via is a real cost for no electrical gain. The README says what a
reviewer's two options are.
The four `courtyards_overlap` errors this board reported before are gone with
the courtyard fix in absmach#266: the mechanical parts were reserving their feature
size instead of their courtyard.
What else is left is in the README's Limitations, and the one worth reading is
absmach#275: four of this board's parts declare a 5 V 100 mA envelope on a 12 V
1.5 A rail, which is placeholder registry data rather than a datasheet figure.
Until that is corrected the board's current capability cannot be checked by
anything but a reader.
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Superseded by #387 which adds proper qualification package, exported KiCad files, and images. |
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Superseded by #387. |
What type of PR is this?
This is a feature.
What does this do?
Adds
protected_power_entry: Q1 reverse-polarity PFET, D1 SMAJ15A, MP2307 5 V buck, TPS22918 switch, AMS1117 3.3 V.Which issue(s) does this PR fix/relate to?
Resolves #262. Related Issue #39.
Have you included tests for your changes?
No. The board is data; the README records
kicad-cliDRC, closed nets and netlist checks.Did you document any new/modified feature?
Yes. README states the no-MCU exception, measured results and limitations;
agent-run/holds prompt and tool calls.Notes
Stacked on #324 (agent-written parts); needs #266 for two parts. Three exports match after zone-fill ids.