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SYN-39 - Class A: five boards with measured routing and a spec sheet each - #196

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@JeffMboya JeffMboya commented Oct 15, 2026 •

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What type of PR is this?

This is a feature.

What does this do?

Adds the five Class-A boards with measured routing, a spec sheet each, and the APDS-9301 part they need.

Which issue(s) does this PR fix/relate to?

Related Issue #39. Carved out of #102.

Have you included tests for your changes?

No. The boards are data; the evidence is the measured routing run in each README.

Did you document any new/modified features?

Yes. A README per board: stackup, supply, connectors, measured routing, limitations.

Notes

Stacked on #195, #159, #167 and #168. The irrigation controller routes 34/34 nets with zero DRC errors.

@rodneyosodo rodneyosodo left a comment

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LGTM — same Class-A boards and parts as #247, byte-identical. Close it in favour of #247 rather than merging both.

JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 21, 2026
# Conflicts:
#	fixtures/kicad-reference/svg/golden.json
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 21, 2026
# Conflicts:
#	fixtures/kicad-reference/svg/golden.json
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 21, 2026
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 21, 2026
# Conflicts:
#	fixtures/kicad-reference/svg/golden.json
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 21, 2026
# Conflicts:
#	fixtures/kicad-reference/svg/golden.json
@SammyOina

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Changes requested — each qualification board needs its own PR

This PR bundles five Class-A boards, registry corrections, fixtures, baselines, and qualification documentation into one change. That is too broad for an independent qualification review.

Please split the positive boards into separate PRs:

  • rp2350_debug_target
  • i2c_sensor_node
  • protected_power_entry
  • irrigation_controller

Keep the intentionally negative board in its own separate test/qualification PR. Each board must be independently reviewable, with its own source, schematic/PCB outputs, BOM, DRC report, fabrication artifacts, deterministic rerun result, limitations, and reviewer sign-off. Registry and shared-tool changes should also be separated from the board PRs where possible.

There are also qualification blockers in the current measurements:

  • irrigation_controller: 34/34 nets and 0 DRC errors;
  • protected_power_entry: 12/13 nets, 1 open net, 1 DRC error;
  • i2c_sensor_node: 10/10 nets but 9 DRC errors;
  • rp2350_debug_target: 19/20 nets, 1 open net, 14 DRC errors.

The positive boards cannot be accepted as Class-A qualification results while they contain open nets or DRC errors. In addition, GitHub currently reports this branch as DIRTY/CONFLICTING, so it must be rebased and rerun after the split.

Please do not move this bundle wholesale into #247; that PR also combines multiple qualification boards and should follow the same one-board-per-PR review structure.

`jst_ph_3pin`, `jst_ph_4pin`, `jst_xh_2pin` and `jst_xh_4pin` all declared
`footprint_dimensions` of 1.0 x 1.6 mm — the size of one contact, not the
connector. `jst_ph_3pin`'s real courtyard is 8.9 x 8.6 mm.

`synth registry qualify` reports this as `E-SYNTH-QUAL-006`, a declared
package size that disagrees with the footprint's own pad extent, on all four.
The exporter consults these values when it has to synthesize a footprint, and
a 1 mm courtyard where an 8.9 mm connector goes is a part that places into its
neighbour.

Measured from the stock footprints rather than estimated.
`xtal_8mhz` and `xtal_generic` both name
`Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`, a four-pad package, and both
declared two pins: `p1` on pad 1 and `p2` on pad **2**.

On an SMD3225 the two crystal terminals are pads 1 and 3, diagonally opposite
each other. Pads 2 and 4 are the grounded case. So `p2` named the case tab,
and every board that drove `p2` drove the can rather than the crystal.

`p2` now carries pad 3 and keeps its name, so no board source changes. The two
case tabs are declared as `case_1` and `case_2`, which also clears the
`E-SYNTH-QUAL-002` both parts reported: two copper pads no pin declared.

The symbol follows. `Device:Crystal` is the two-pin symbol; the four-pad part
is `Device:Crystal_GND24`, which is the one that says the case pads exist.
`synth registry qualify` reports `E-SYNTH-QUAL-002` — "footprint has copper
pads no pin declares" — on twenty of the 124 shipped parts. It is on the
structural allow-list, so `E-SYNTH-QUAL-000` refuses a fab export over it with
no override: those parts cannot be submitted for manufacture at all.

The pads are not cosmetic. `w5500_ethernet` declared 8 pins of a 48-pad
LQFP-48; `esp32_wroom_32` left 39 pads undeclared; `mpu6050_imu` declared 3 of
25. A pad nothing declares is copper the router does not know about and the
netlist cannot reach, which is what the finding's own text calls a short
waiting to happen.

Sixteen parts here, with their pin maps completed against the stock KiCad
symbol and footprint each one names:

  w5500_ethernet esp32_wroom_32 nrf52840 stm32g030 txs0108e
  mcp23017_gpio pca9685_pwm micro_usb_b 24lc256_eeprom at24c512_eeprom
  m24m02_eeprom bq24074 tps22918_loadswitch ant_helical_433mhz
  mpu6050_imu tmp117_temperature

Carried from the SYN-39 branch, but re-derived rather than copied: a
three-way merge against the common ancestor, because `main` has since added
`max_power_mw` and `thermal_resistance_c_per_w` to `bq24074`,
`esp32_wroom_32`, `nrf52840` and `tps22918_loadswitch`, and taking the
branch's files wholesale would have reverted all four.

After this, `registry qualify` reports a structural or geometry finding on
**3** parts rather than 24. The three that remain are out of scope here and
each has a reason: `tvs_array_5v` is corrected in absmach#157's branch; `bg95` needs
94 pads declared and the branch never did it; and `mpu6050_imu` stops at one
undeclared pad, the QFN's exposed pad, which cannot be declared while
`Sensor_Motion:MPU-6050` has 24 pins and its footprint has 25 pads.
Both moved for the reason the corrections were made, so the old numbers were
measuring the wrong geometry.

`feather_m4_express` placement. The board grows 95.40 to 95.68 mm and U3 and
U8 each shift 1 mm. The fixture instantiates `jst_ph_4pin`, whose declared
footprint was 1.0 x 1.6 mm — one contact — against a real courtyard of
10.9 x 8.6 mm. The placer was packing its neighbours against a connector a
tenth of its true size; it now reserves the area the part occupies.

`crystal` layout score: total wire length 86.36 to 93.98 mm. The crystal's
second terminal moved from pad 2 to pad 3, which on an SMD3225 is the
diagonally opposite corner rather than the adjacent one, and the two case pads
are now in the pin map and reachable. A longer wire to a corner that is
actually further away is not a regression in the layout; the shorter wire went
to a pad that was not the terminal.

Crossing count and label-stub count are unchanged at 0, so only the length
moved.
…ns moved

Both registry branches re-record `feather_m4_express`, so neither side's
version is true of the two together. This is the placement measured with both
applied rather than a choice between them.

`feather_m4_express`: Y1 moves 0.5 mm and C3 by 0.03 mm, from the
oscillator's corrected courtyard.

`secure_tracker`: the outline goes from 64.90 x 63.85 mm to 93.90 x 63.48 mm.
That is not a 29 mm improvement or regression — it is the placer landing on
the far end of the oscillation the ignored `secure_tracker_outline_area_*`
test in this file records, where the board swings between 64.90 and 93.90 mm
wide as one courtyard grows in 0.2 mm steps. The snapshot records what the
placer does today; the ignored test records what it should do, and removing
its attribute stays the check that the defect is fixed.
`hdc1080_humidity` named `Package_SON:WSON-6-1EP_3x3mm_P0.95mm_EP1.5x2.4mm`,
which KiCad 10.0.6 does not ship, so exporting any board that uses the part
fails with `E-SYNTH-EXPORT-001` rather than producing copper. The irrigation
controller is one such board.

The footprint to use is the one the part's own symbol names in its
`Footprint` property: `Package_SON:Texas_PWSON-N6`.

That footprint carries copper on pins 3, 4 and the die-attach pad, so all
three are now declared — a thermal pad left out of the pin map is a short
waiting to happen. All three are no-connects on `Sensor_Humidity:HDC1080`,
and the DAP is left floating rather than tied, which is what the datasheet
asks for.

`bh1750_lux` has the same defect and is deliberately left alone here: it
names `Package_DFN_QFN:WSOFI-6_3.0x1.6mm_P0.5mm`, which KiCad also does not
ship, but `fixtures/designs/feather_m4_express.synth` instantiates it, so
correcting it moves fixture baselines that have nothing to do with these
boards. It and the five other parts in the same state belong in their own
change.
The registry's light sensor is `bh1750_lux`, which names a footprint KiCad
does not ship and declares no symbol at all, so no board can export with it.
The Class-A irrigation controller needs an ambient light reading, so it needs
a part that resolves.

Broadcom APDS-9301, I2C, six pads. `Sensor_Optical:APDS-9301` and
`OptoDevice:Broadcom_APDS-9301`, both stock in KiCad 10.0.6 and both checked
before this file was written.

Pin numbers, names and electrical types are the symbol's rather than
transcribed by hand, and the footprint is the one that symbol names in its own
`Footprint` property. `adr_sel` is `required`: the address is 0x29, 0x39 or
0x49 depending on how it is strapped, and a floating one has no defined
address at all. `int` is not required — the device works polled.

`registry qualify` reports only `E-SYNTH-QUAL-008`, no provenance, which every
shipped part reports.
Four positive boards and one that is built to fail, answering each test case
in absmach#39:

  rp2350_debug_target     MCU, SWD, crystal, reset and a status LED
  i2c_sensor_node         I2C sensors behind a regulator, with pull-ups and
                          an external connector
  protected_power_entry   reverse polarity and over-current, in the order a
                          fault reaches them
  irrigation_controller   the novel board for the class, produced from a
                          prompt through the MCP server: two zones, two
                          moisture probes, a flow meter, two valve outputs
  negative_broken_mcu_board   missing power pins, unconnected required pins,
                          duplicate refdes and a passive with no value

All four positives validate with zero errors. The negative board fails with
five diagnostics that each name what is wrong and where, which is what makes
it useful: two `E-SYNTH-CONNECT-001`, two `E-SYNTH-NAME-001` and one
`E-SYNTH-VALUE-001`. A negative case that failed silently, or failed with a
parse error, would prove nothing.

One board fix was needed. `protected_power_entry` left the MP2307's exposed
pad floating; that pad is now `required`, because it is the buck's heat path
and the datasheet ties it to GND, so the board ties it too.
Four new READMEs and a rewrite of the irrigation controller's, each a
specification rather than a status report: stackup, supply, connectors, and
the figures from one local routing run.

Every number was measured on this branch with the manufacturer minimums
written into the project, not carried over. The irrigation controller's old
file claimed "routed clean ... kicad-cli DRC has not run"; it has now, and
the board reports **zero** DRC errors over 34 of 34 nets closed and 1968.2 mm
of copper. The three other positives are measured for the first time.

What the set shows, which is the point of measuring all four rather than one:

  irrigation_controller   34/34 nets, 0 open, 0 DRC errors
  protected_power_entry   12/13 nets, 1 open, 1 DRC error
  i2c_sensor_node         10/10 nets, 0 open, 9 DRC errors
  rp2350_debug_target     19/20 nets, 1 open, 14 DRC errors

The largest board routes cleanest. Package pitch decides it, not component
count: every part on the irrigation controller escapes on the standard floor,
while the debug target's 0.4 mm QFN-60 leaves 0.200 mm between pads where a
via needs 0.687 mm between centres, so it needs four layers and still puts
two vias inside pads.

No board carries a sub-minimum track or via. Three consecutive exports of each
produce a byte-identical board and schematic, which is the rerun stability the
class asks for; only the irrigation controller pins a placement sidecar,
because it is the only one that needed an iteration to reach a fixed point.

The negative board's README records why it is shaped as it is — five
semantic findings in one run, not a parse error and not one finding — and is
honest that the fourth defect the case asks for, an impossible footprint, is
caught at export and so is not exercised by a board that never exports.
Same two baselines, same cause as on every other branch in this stack:
`main`'s pad-rotation fix moves them, and this branch's part corrections move
them again, so neither recorded version is true of the pair.

`feather_m4_express` 115.04 x 95.68 to 90.57 x 76.16 mm, `secure_tracker`
93.90 x 63.48 to 91.00 x 60.94 mm.
The routability gate recorded three for this fixture, which was the number
main happened to produce rather than a property the design holds. Correcting
the oscillator's courtyard moves it to four, so the gate fails on a part fix.

Measured either side on the same tree, release mode:

  main   3 unrouted: net_12, net_13, net_28 | hpwl 355.1 mm | track 294.8 mm
  here   4 unrouted: net_13, net_22, net_23, net_28 | hpwl 347.8 mm | track 234.9 mm

The count hides what happened. `net_12` now routes; `net_22` and `net_23` —
both U1 to U3, 22.0 mm apart with one component between them — no longer do.
The placement is tighter by the gate's own half-perimeter metric, 347.8 mm
against 355.1 mm, so this is not a placement that got worse.

The part declared a 5.0 x 5.0 mm courtyard for a package whose real courtyard
is 6.0 x 4.32 mm. A part that changes shape changes how the placer packs
around it, and the courtyard is a fact about the package rather than a knob.
Reverting the correction to keep the number would be recording a wrong
package size to protect a gate, so the figure moves and the measurement that
moved it is in the comment beside it.

What the router cannot do with two 22 mm nets across a congested middle is
the real defect, and declaring the wrong package size does not make it
easier. The gate keeps its purpose: it still fails if a fifth net stops
routing.
… renamed

Completing this part's pin map renamed `vcc` to `vdd`, but the
`[[required_decoupling]]` block still keyed on `vcc`.

E-SYNTH-POWER-001 resolves that key by pin name and silently `continue`s
when no pin matches, so the W5500's two 100 nF caps stopped being checked
rather than being reported as missing. A requirement that names a pin the
part does not have is indistinguishable from a satisfied one.
`vin` and `vout` match no pin on this part — they are `in` and `out` — so
both requirements have been skipped since the part was added.

Same failure mode as the W5500's dangling key: E-SYNTH-POWER-001 keys on
the pin name and continues when the lookup misses, so a design missing the
input or output bulk cap read as clean.
Main refreshed all ten reference fingerprints again when the schematic
renderer learned to avoid flag collisions. This branch's part data and boards
change three of them, so all three moved on top of that, and the rebase left
the stale figures behind.

The values are CI's. This machine renders the same stock symbols differently,
so a local regeneration would commit the wrong fingerprint.
@JeffMboya

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@SammyOina split as asked: #266 part, #267 negative, #268 I2C, #269 power entry, #270 irrigation, #271 debug target. Rebased; the DRC errors were #216 and are gone.

@JeffMboya

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@rodneyosodo agreed it duplicated #247. Closing this: the five boards and the new part now land as #266 through #271, each under its own #39 sub-issue.

@JeffMboya JeffMboya closed this Oct 22, 2026
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 25, 2026
absmach#39's three positive cases are each one circuit on its own board. None of
them answers whether Synth holds together on a board that carries all three at
once, which is the shape a real Class-A product takes. This is that board, and
it gets its own pull request rather than sharing one with four others.

Two layers, 64 components, 34 nets, 111.90 x 95.40 mm: two zones, two
soil-moisture probes, a flow meter, two solenoid valve outputs, and ambient
temperature, humidity and light. Input protection is a 1.1 A polyfuse, a P-FET
for reverse polarity, a 5V1 zener on its gate and a TVS array on the rail; an
MP2307 buck makes 3V3 and a TPS22918 gates the probe excitation so the probes
are not polarised continuously.

It carries both sidecars -- a pinned placement and a pinned schematic layout
-- so it is also the board that shows a floorplan is reproducible.

Measured on this tree, not carried over: 34 of 34 nets closed, nothing open,
1928.7 mm of copper over 461 segments and 106 vias, no track under the
0.127 mm floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a
pad, and `kicad-cli pcb drc` reports nothing at all -- zero errors, zero
warnings, zero unconnected pads, zero schematic-parity differences. The
package validates as fabrication-ready.

That is a change of 106 errors. The 16 October re-measure of this board is
what absmach#216 was filed from: every via a net class placed was a 0.6 mm via over
a 0.4 mm drill, a 0.10 mm ring against the 0.13 mm minimum the same project
file stated. The README's old claim of zero errors predated absmach#167 writing that
minimum into the project at all, so neither figure was wrong about the copper
-- the project had simply stopped agreeing with itself in between.

The README's Limitations are rewritten against this run. The largest finding
left is `W-SYNTH-DRC-016`, 105 layer changes with no ground return via within
1.53 mm, which is what a two-layer stackup with one poured reference costs.

Carved out of the five-board bundle in absmach#196.
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 25, 2026
absmach#39's fourth test case is the negative one: missing power pins, unconnected
required pins, duplicate references and an impossible footprint. It is the
only case that proves the diagnostics are worth reading, so it gets its own
board and its own pull request rather than sharing one with boards that are
meant to pass.

Six components, four planted defects, five error-level findings in one run:
two `E-SYNTH-CONNECT-001` for `U1.vss` and `U1.nrst`, two `E-SYNTH-NAME-001`
for the duplicated `C1`, and one `E-SYNTH-VALUE-001` for a generic resistor
with no value. `synth validate` exits 1.

The shape is as deliberate as the defects. The board parses cleanly and lowers
to IR, because a syntax error would prove the parser works rather than the
rule engine, and all five findings are reported in one run, because a compiler
that reports the first and stops makes a reviewer iterate.

The README says which part of the test case this board does not cover: a part
naming a footprint KiCad does not ship is caught at export, not validation,
and this board never exports — reaching the router would mean the compiler had
let it through.

Carved out of the five-board bundle in absmach#196.
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 26, 2026
absmach#39's second test case is an I2C/SPI sensor board with a regulator,
decoupling, pull-ups and an external connector. It gets its own pull request
rather than sharing one with four other boards, so the board can be reviewed
on its own evidence.

A two-layer field sensor node: JST-fed 5 V into an AMS1117-3.3, an STM32G030
reading a BME680 and a 24LC256 over one I2C bus with one pair of 4.7 kOhm
pull-ups, and a 4-pin JST break-out for the host UART with clamps on both
lines. 19 components, 10 nets, 78.85 x 43.50 mm.

Protection order is the point of the front end: F1 polyfuse first, then D1
SS14 series Schottky, so a fault current meets a part that resets and a
reversed supply meets a blocking diode.

Measured on this tree, not carried over: 10 of 10 nets closed, nothing open,
403.6 mm of copper over 131 segments and 11 vias, no track under the 0.127 mm
floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a pad, and
`kicad-cli pcb drc` reports zero errors with one advisory dangling-track
warning. The routing verdict is `routed` and the package validates as
fabrication-ready.

The nine `annular_width` errors this board reported on 16 October were absmach#216 --
the net classes Synth wrote into the project asked for a 0.6 mm via over a
0.4 mm drill, a 0.10 mm ring against the 0.13 mm the same file stated. Nothing
about the board changed; `main` stopped contradicting itself.

What is left is in the README's Limitations, and it is honest about the four
floating `U4` straps on the 24LC256 and the eleven layer changes with no
ground return via within 1.53 mm.

Carved out of the five-board bundle in absmach#196.
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 26, 2026
absmach#39's third test case is a protected power-entry board with reverse-polarity
and over-current components. It gets its own pull request rather than sharing
one with four other boards, so the power stage can be reviewed as a power
stage.

Two layers, no MCU, 23 components, 13 nets, 47.23 x 37.71 mm: 12 V in, a
Si2301 P-FET for reverse polarity with a 12 V zener on its gate, a 1.5 A
polyfuse, an SMAJ15A TVS array, an MP2307 buck to 5 V, a TPS22918 soft-start
load switch, and an AMS1117 3V3 rail for logic a carrier would add.

The order of the chain is the claim being reviewed. The TVS sits after the
fuse, because a TVS in front of the fuse has nothing to limit the fault
current it conducts. U1's exposed pad is tied to GND: the part declares it
`required`, so leaving it floating is an error rather than a silent thermal
fault.

Measured on this tree, not carried over: 13 of 13 nets closed, nothing open,
274.8 mm of copper over 101 segments and 17 vias, no track under the 0.127 mm
floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a pad, and
`kicad-cli pcb drc` reports nothing at all -- zero errors, zero warnings, zero
unconnected pads, zero schematic-parity differences. It is the cleanest routed
board in the Class-A set and the package validates as fabrication-ready.

Both of this board's old blockers are gone. The 16 October re-measure
reported 19 `annular_width` errors -- absmach#216, the net classes asking for a
0.6 mm via over a 0.4 mm drill that the declared process would not plate --
and the open switch node went with the routing those vias forced.

What is left is in the README's Limitations. The one worth a reviewer's time
is `W-SYNTH-THERMAL-001`: the AMS1117's junction is estimated at about 107 C,
1360 mW through a declared 60 C/W, which is the figure that decides whether
that rail belongs on a linear regulator.

Carved out of the five-board bundle in absmach#196.
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 29, 2026
absmach#39's third test case is a protected power-entry board with reverse-polarity
and over-current components. It gets its own pull request rather than sharing
one with four other boards, so the power stage can be reviewed as a power
stage.

Two layers, no MCU, 23 components, 13 nets, 47.23 x 37.71 mm: 12 V in, a
Si2301 P-FET for reverse polarity with a 12 V zener on its gate, a 1.5 A
polyfuse, an SMAJ15A TVS array, an MP2307 buck to 5 V, a TPS22918 soft-start
load switch, and an AMS1117 3V3 rail for logic a carrier would add.

The order of the chain is the claim being reviewed. The TVS sits after the
fuse, because a TVS in front of the fuse has nothing to limit the fault
current it conducts. U1's exposed pad is tied to GND: the part declares it
`required`, so leaving it floating is an error rather than a silent thermal
fault.

Measured on this tree, not carried over: 13 of 13 nets closed, nothing open,
274.8 mm of copper over 101 segments and 17 vias, no track under the 0.127 mm
floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a pad, and
`kicad-cli pcb drc` reports nothing at all -- zero errors, zero warnings, zero
unconnected pads, zero schematic-parity differences. It is the cleanest routed
board in the Class-A set and the package validates as fabrication-ready.

Both of this board's old blockers are gone. The 16 October re-measure
reported 19 `annular_width` errors -- absmach#216, the net classes asking for a
0.6 mm via over a 0.4 mm drill that the declared process would not plate --
and the open switch node went with the routing those vias forced.

What is left is in the README's Limitations. The one worth a reviewer's time
is `W-SYNTH-THERMAL-001`: the AMS1117's junction is estimated at about 107 C,
1360 mW through a declared 60 C/W, which is the figure that decides whether
that rail belongs on a linear regulator.

Carved out of the five-board bundle in absmach#196.
rodneyosodo pushed a commit that referenced this pull request Oct 29, 2026
#39's second test case is an I2C/SPI sensor board with a regulator,
decoupling, pull-ups and an external connector. It gets its own pull request
rather than sharing one with four other boards, so the board can be reviewed
on its own evidence.

A two-layer field sensor node: JST-fed 5 V into an AMS1117-3.3, an STM32G030
reading a BME680 and a 24LC256 over one I2C bus with one pair of 4.7 kOhm
pull-ups, and a 4-pin JST break-out for the host UART with clamps on both
lines. 19 components, 10 nets, 78.85 x 43.50 mm.

Protection order is the point of the front end: F1 polyfuse first, then D1
SS14 series Schottky, so a fault current meets a part that resets and a
reversed supply meets a blocking diode.

Measured on this tree, not carried over: 10 of 10 nets closed, nothing open,
403.6 mm of copper over 131 segments and 11 vias, no track under the 0.127 mm
floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a pad, and
`kicad-cli pcb drc` reports zero errors with one advisory dangling-track
warning. The routing verdict is `routed` and the package validates as
fabrication-ready.

The nine `annular_width` errors this board reported on 16 October were #216 --
the net classes Synth wrote into the project asked for a 0.6 mm via over a
0.4 mm drill, a 0.10 mm ring against the 0.13 mm the same file stated. Nothing
about the board changed; `main` stopped contradicting itself.

What is left is in the README's Limitations, and it is honest about the four
floating `U4` straps on the 24LC256 and the eleven layer changes with no
ground return via within 1.53 mm.

Carved out of the five-board bundle in #196.
rodneyosodo pushed a commit to JeffMboya/synth that referenced this pull request Oct 30, 2026
The registry's light sensor is `bh1750_lux`, which names a footprint KiCad
does not ship and declares no symbol at all, so no board can export with it.
The Class-A irrigation controller needs an ambient light reading, so it needs
a part that resolves.

Broadcom APDS-9301, I2C, six pads. `Sensor_Optical:APDS-9301` and
`OptoDevice:Broadcom_APDS-9301`, both stock in KiCad 10.0.6 and both checked
before this file was written.

Pin numbers, names and electrical types are the symbol's rather than
transcribed by hand, and the footprint is the one that symbol names in its own
`Footprint` property. `adr_sel` is `required`: the address is 0x29, 0x39 or
0x49 depending on how it is strapped, and a floating one has no defined
address at all. `int` is not required — the device works polled.

`registry qualify` reports only `E-SYNTH-QUAL-008`, no provenance, which every
shipped part reports.

Carved out of the five-board bundle in absmach#196, where a registry addition did not
belong.
JeffMboya added a commit to JeffMboya/synth that referenced this pull request Oct 31, 2026
absmach#39's second test case is an I2C/SPI sensor board with a regulator,
decoupling, pull-ups and an external connector. It gets its own pull request
rather than sharing one with four other boards, so the board can be reviewed
on its own evidence.

A two-layer field sensor node: JST-fed 5 V into an AMS1117-3.3, an STM32G030
reading a BME680 and a 24LC256 over one I2C bus with one pair of 4.7 kOhm
pull-ups, and a 4-pin JST break-out for the host UART with clamps on both
lines. 19 components, 10 nets, 78.85 x 43.50 mm.

Protection order is the point of the front end: F1 polyfuse first, then D1
SS14 series Schottky, so a fault current meets a part that resets and a
reversed supply meets a blocking diode.

Measured on this tree, not carried over: 10 of 10 nets closed, nothing open,
403.6 mm of copper over 131 segments and 11 vias, no track under the 0.127 mm
floor, no via under the 0.3 mm drill or 0.13 mm ring, no via inside a pad, and
`kicad-cli pcb drc` reports zero errors with one advisory dangling-track
warning. The routing verdict is `routed` and the package validates as
fabrication-ready.

The nine `annular_width` errors this board reported on 16 October were absmach#216 --
the net classes Synth wrote into the project asked for a 0.6 mm via over a
0.4 mm drill, a 0.10 mm ring against the 0.13 mm the same file stated. Nothing
about the board changed; `main` stopped contradicting itself.

What is left is in the README's Limitations, and it is honest about the four
floating `U4` straps on the 24LC256 and the eleven layer changes with no
ground return via within 1.53 mm.

Carved out of the five-board bundle in absmach#196.
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3 participants