[nyagamunene]

Refs #67 (under #38). Draft: no reviewer has signed this board off.

Purpose

A switching-regulator board for the Class B set: 24 V in, 3.3 V out, TI TPS54202 with a Bourns SRN6045TA inductor, input PTC fuse, reverse-block Schottky, TVS, undervoltage lockout on EN, power LED. A twin with the feedback taken from the switch node is flagged by E-SYNTH-POWER-011 (#56). This is #38's test case 1 only; the analog front end, the USB/Ethernet board and the other negative cases live in other boards.

Picture

What

• qualification/class-b/buck/: buck.synth, the board-mm placement sidecar, buck_neg_fb_sw.synth, QUALIFICATION.md (A: checked by tools, B: needs an expert, C: Class B: verify mixed-signal/RF output and capability boundaries #38 traceability, D: the matrix row), README with datasheet values per part, kicad/ (project, BOM, pick-and-place, 22 Gerbers + job file, drill), reports/ (two release reports, DRC, ERC, routing, connectivity, registry qualification), images/ (3D top and bottom, schematic), SHA256SUMS.
• 7 registry parts (TPS54202, SRN6045TA-100M, SS36, SMBJ26A, MF-MSMF110/33X, JST B2B-XH-A, 8x10 SMD electrolytic), all UNVERIFIED (no reviewer).
• No Rust changes.

State (re-run 2026-10-24 on main 1eac8a1, release build, KiCad 10.0.7, FreeRouting 2.4.1, OpenJDK 25.0.5)

• synth validate: 0 errors, 14 warnings (8 part-unverified, 3 SCHEM-003, 1 SCHEM-005, 1 anomaly, 1 supply). The negative twin exits 1 with E-SYNTH-POWER-011 and 13 warnings.
• Routed (--router free-routing): 10 nets, 0 open, 51 segments, 15 vias, 155.16 mm. release_ready true for the source/DRC gate.
• The fab package is not a release: release_ready false, production_status untrusted, because 7 parts have no reviewer. Both reports are committed (reports/release.json, reports/release-fab.json), so neither answer is hidden.
• KiCad DRC: 0 errors, 0 unconnected, 20 warnings, all library links. ERC: 0 errors, 54 warnings, all library links.
• Manufacturing exports generated this time: 22 Gerbers plus the job file (4 copper layers), PTH drill 19 holes, NPTH none, BOM and pick-and-place, all hashed. Nothing was fabricated or opened in a fab's DFM tool.
• Outline 58.0 x 32.6 mm (1891 mm2). It was 63.0 x 37.6 mm; the difference is NOISSUE - Shrink auto-fitted board area #272's 1.5 mm edge rim, not a layout change — every part position is identical and the sidecar matches the routed board within 0.01 mm.
• Three exports gave byte-identical .kicad_pcb and .kicad_sch, including the one with the fab flags.
• One advisory finding, W-SYNTH-DRC-016: the +3V3 via at (35.97, 14.43) mm changes layers with no ground return via within 0.64 mm. The report calls it "net 3", which is Synth's numbering; in the .kicad_pcb net 3 is FB.

Why this board is its own case

• QUALIFICATION.md section C maps every #38 "Check exactly" line to a verdict for this board, including the lines that do not apply (no differential pair, no stackup claim) and the two features it cannot carry (power-good, thermal copper).
• Section B cites the compiler's own capability ids where a claim rests on a gap: thermal_relief_analysis, power_sequencing_and_power_good, split_ground_planes, return_path_and_layer_transition_analysis. A reviewer can diff those against synth capability list --json.
• The A rows are new measurements: the schematic netlist equals the source net for net, the Gerber and drill sets are checked for layer and hole counts, and the placement sidecar is verified against the routed board.
• Section D carries the exact [[board]] row for qualification/matrix.toml. expect and expect_fab are deliberately absent: synth check always selects KiCadRoutingTools at this revision and no checkout was available to measure it, so inventing the values would break the matrix's "measured, not assumed" rule.

Not true yet

• Overvoltage: NEEDS EXPERT. SMBJ26A conducts at 28.9 to 31.9 V; TPS54202 absolute maximum is 30 V. The TVS clamps surge energy only, not a sustained 28 to 32 V rail.
• Rated 1 A out, not 2 A. By my estimate the junction is about 133 C at 1 A and 70 C ambient (above the 125 C limit). Thermal copper and vias are not modelled by Synth, whose capability descriptor says so.
• Power-good is UNSUPPORTED (the part has no PG pin). Capacitor derating, crossover and stability are UNVERIFIED.
• Schematic is readable but not tidy: 1 overlapping text pair, 5 wire crossings, mean passive-to-pin distance 83.8 mm; the +3V3 run past the BOOT pin reads like a boot capacitor at print size, though the netlist is correct.
• No mounting holes, so the board cannot be fixed down as it stands.
• QUALIFICATION.md B1 to B8 and A2/A9 are the rows that decide a Class B bar; they are open.

Not verified

• Nothing powered, built or measured. 85% efficiency is an assumption.
• SOT-23-6 footprint not compared with the TI drawing. No reviewer. LCSC numbers and availability not checked.
• Hash reproducibility on another machine depends on FreeRouting 2.4.1, the JVM and KiCad 10.0.7.

Matrix

qualification/matrix.toml is not on main yet (it arrives with #247), so this board cannot be added to it here. The row it will declare is in QUALIFICATION.md section D; it becomes checkable once synth check can select an engine and a KiCadRoutingTools checkout is pinned for CI.

[rodneyosodo]

LGTM. Board validates and the negative fixture errors with E-SYNTH-POWER-011 as claimed. Coordination note: once #247 lands this board needs its own qualification/matrix.toml row or it never runs in the gate.