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Support misaligned load/store in executor memory #625
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cd77cef
Support misaligned load/store in executor memory
gabrielbosio a988fbe
Add misaligned load/store regression tests
gabrielbosio fe1e1b5
Tighten misalign asm test comments
gabrielbosio 821137a
Drop single-cell fast path from load_half/store_half
gabrielbosio 74922ff
Trap misaligned PC in instruction fetch
gabrielbosio a6e15d8
Verify loaded value in misalign load tests
gabrielbosio 210bbd7
Restore load_half/store_half fast paths
gabrielbosio 6bac80b
Use natural alignment in load/store fast paths
gabrielbosio 0d309b7
Merge branch 'main' into fix_misalign_memory_access
gabrielbosio 5f0ad40
Drop infallible .unwrap() in load_half fast path
gabrielbosio 95ca239
Verify stored bytes in misalign store tests
gabrielbosio b9ac3b8
Reject misaligned load/store crossing u64::MAX
gabrielbosio b1a88d6
Document why aligned doubleword +4 needs no overflow guard
gabrielbosio cc29d49
Merge remote-tracking branch 'origin/main' into fix_misalign_memory_a…
gabrielbosio 227b2e7
Merge branch 'main' into fix_misalign_memory_access
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned LD: 8-byte load at address 33. | ||
| li t0, 32 | ||
| li t1, 0x80FF1234 | ||
| sw t1, 0(t0) | ||
| li t1, 0xDEADBEEF | ||
| sw t1, 4(t0) | ||
| li t1, 0x000000AA | ||
| sw t1, 8(t0) | ||
| ld a0, 1(t0) | ||
| li t2, 0xAADEADBEEF80FF12 | ||
| bne a0, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned LH: 2-byte load at address 35. | ||
| li t0, 32 | ||
| li t1, 0x3412FF80 | ||
| sw t1, 0(t0) | ||
| li t1, 0x000000AA | ||
| sw t1, 4(t0) | ||
| lh a0, 3(t0) | ||
| li t2, 0xFFFFFFFFFFFFAA34 | ||
| bne a0, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned LHU: 2-byte load at address 35. | ||
| li t0, 32 | ||
| li t1, 0x3412FF80 | ||
| sw t1, 0(t0) | ||
| li t1, 0x000000AA | ||
| sw t1, 4(t0) | ||
| lhu a0, 3(t0) | ||
| li t2, 0xAA34 | ||
| bne a0, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned LW: 4-byte load at address 33. | ||
| li t0, 32 | ||
| li t1, 0x80FF1234 | ||
| sw t1, 0(t0) | ||
| li t1, 0x000000AA | ||
| sw t1, 4(t0) | ||
| lw a0, 1(t0) | ||
| li t2, 0xFFFFFFFFAA80FF12 | ||
| bne a0, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned LWU: 4-byte load at address 33. | ||
| li t0, 32 | ||
| li t1, 0x80FF1234 | ||
| sw t1, 0(t0) | ||
| li t1, 0x000000AA | ||
| sw t1, 4(t0) | ||
| lwu a0, 1(t0) | ||
| li t2, 0xAA80FF12 | ||
| bne a0, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned SD: 8-byte store at address 65. | ||
| li t0, 64 | ||
| li t1, 0x123456789ABCDEF0 | ||
| sd t1, 1(t0) | ||
| lwu a1, 0(t0) | ||
| li t2, 0xBCDEF000 | ||
| bne a1, t2, .Lfail | ||
| lwu a1, 4(t0) | ||
| li t2, 0x3456789A | ||
| bne a1, t2, .Lfail | ||
| lwu a1, 8(t0) | ||
| li t2, 0x00000012 | ||
| bne a1, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
|
gabrielbosio marked this conversation as resolved.
|
||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned SH: 2-byte store at address 67. | ||
| li t0, 64 | ||
| li t1, 0xAA12 | ||
| sh t1, 3(t0) | ||
| lwu a1, 0(t0) | ||
| li t2, 0x12000000 | ||
| bne a1, t2, .Lfail | ||
| lwu a1, 4(t0) | ||
| li t2, 0x000000AA | ||
| bne a1, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Misaligned SW: 4-byte store at address 65. | ||
| li t0, 64 | ||
| li t1, 0xDEADBEEF | ||
| sw t1, 1(t0) | ||
|
gabrielbosio marked this conversation as resolved.
|
||
| lwu a1, 0(t0) | ||
| li t2, 0xADBEEF00 | ||
| bne a1, t2, .Lfail | ||
| lwu a1, 4(t0) | ||
| li t2, 0x000000DE | ||
| bne a1, t2, .Lfail | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall | ||
| .Lfail: | ||
| li a0, 1 | ||
| li a7, 93 | ||
| ecall | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| .attribute 5, "rv64i2p1_m2p0" | ||
| .globl main | ||
| main: | ||
| # Jump to PC = 2 (not 4-aligned). | ||
| jalr zero, zero, 2 | ||
| li a0, 0 | ||
| li a7, 93 | ||
| ecall |
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