HCUS – Hardware Control Unit Simulator for a Mini Processor

Overview

HCUS (Hardware Control Unit Simulator) is a Verilog-based simulation project that demonstrates the working of a hardware control unit for a simple mini processor architecture.
The project focuses on implementing the processor’s Finite State Machine (FSM) driven control logic and verifying instruction execution through waveform simulation using GTKWave.

The simulator models how a processor control unit generates internal control signals for different instructions such as:

• NOP
• ADD
• SUB
• LOAD
• STORE

The design is tested using a Verilog testbench and visualized using .vcd waveform files.

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Features

• FSM-based Control Unit Design
• Multi-cycle Instruction Execution
• Verilog HDL Implementation
• Opcode-based Control Signal Generation
• Waveform Verification using GTKWave
• Instruction Fetch / Decode / Execute Simulation
• Supports Arithmetic and Memory Instructions
• Clear State Transitions for Processor Operations

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Objectives

The main goal of this project is to simulate how a processor control unit behaves internally during instruction execution.

This project helps in understanding:

• Processor control logic
• FSM implementation in hardware
• Multi-cycle CPU operation
• Instruction sequencing
• Control signal generation
• Hardware simulation and debugging

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Architecture

The Hardware Control Unit controls different datapath operations by generating control signals according to the current instruction opcode and FSM state.

The system performs operations in stages such as:

1. Instruction Fetch
2. Instruction Decode
3. Execute
4. Memory Access
5. Write Back

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FSM (Finite State Machine) Implementation

The control unit is implemented using a Finite State Machine (FSM) where each state represents a stage of instruction execution.

FSM States

State	Purpose
State 0	Instruction Fetch
State 1	Instruction Decode
State 2	ADD Execution
State 3	SUB Execution
State 4	Memory Address / STORE
State 5	LOAD Memory Read

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Supported Instructions

Instruction	Opcode	Description
NOP	0000	No Operation
ADD	0001	Addition Operation
SUB	0010	Subtraction Operation
LOAD	0011	Load data from memory
STORE	0100	Store data into memory

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Control Signals

The control unit generates several important processor signals:

Signal	Function
pc_inc	Increment Program Counter
mem_read	Enable Memory Read
mem_write	Enable Memory Write
alu_op	Select ALU Operation
reg_write	Enable Register Write
mem_to_reg	Transfer Memory Data to Register
ir_load	Load Instruction Register

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Working Principle

1. Instruction Fetch

The processor fetches the instruction from memory.

Generated signals:

• pc_inc = 1
• mem_read = 1
• ir_load = 1

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2. Instruction Decode

The opcode is decoded and the FSM transitions to the required execution state.

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3. Execute Phase

ADD Instruction

• ALU performs addition
• Register write enabled

SUB Instruction

• ALU performs subtraction
• Result written back to register

LOAD Instruction

• Memory read enabled
• Data transferred to register

STORE Instruction

• Memory write enabled
• Register data stored into memory

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Simulation Output

The project includes waveform verification using GTKWave.

The simulation demonstrates:

• State transitions
• Opcode decoding
• ALU operation changes
• Register write operations
• Memory read/write cycles
• Instruction execution timing

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Waveform Analysis

The waveform confirms proper FSM operation:

• Correct instruction sequencing
• Proper control signal activation
• Multi-cycle execution behavior
• Correct transition between states
• Memory and ALU operations functioning correctly

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Technologies Used

Technology	Purpose
Verilog HDL	Hardware Design
GTKWave	Waveform Visualization
Icarus Verilog	Simulation
FSM Design	Control Logic

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Project Structure

HCUS/
│── control_unit.v
│── control_unit_tb.v
│── control_unit.vcd
│── README.md

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How to Run

Compile

iverilog -o control_unit control_unit.v control_unit_tb.v

Run Simulation

vvp control_unit

Open Waveform

gtkwave control_unit.vcd

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Example Simulation Output

[45.0 ns] State: 1 | Opcode: 0001
[55.0 ns] State: 2 | Opcode: 0001
[75.0 ns] State: 0 | Opcode: 0001 | reg_write: 1

This indicates:

• Instruction decode
• ADD execution
• Result write-back

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Educational Importance

This project is useful for learning:

• Computer Architecture
• Processor Design
• Hardware FSM Design
• CPU Control Logic
• Verilog HDL
• Digital System Simulation

It provides a practical understanding of how real processors coordinate internal operations through a hardware control unit.

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Future Improvements

Possible future extensions:

• Branch Instructions
• Jump Operations
• Pipeline Support
• Hazard Detection
• Interrupt Handling
• Cache Simulation
• Extended Instruction Set
• Microprogrammed Control Unit

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Conclusion

HCUS demonstrates the core working principles of a processor control unit using FSM-based hardware design in Verilog.
The project successfully simulates instruction execution, control signal generation, and state transitions for a mini processor architecture while providing clear waveform verification through GTKWave.