opcode_decoder.v

`timescale 1ns / 1ps

/*
 * Opcode Decoder
 * NOP: 0000, ADD: 0001, SUB: 0010, LOAD: 0011, STORE: 0100
 */
module opcode_decoder (
    input [3:0] Opcode,
    output is_ADD,
    output is_SUB,
    output is_LOAD,
    output is_STORE,
    output is_NOP
);

    // Define opcodes used in the testbench
        parameter OP_NOP   = 4'b0000;
    parameter OP_ADD   = 4'b0001;
    parameter OP_SUB   = 4'b0010;
        parameter OP_LOAD  = 4'b0011;
    parameter OP_STORE = 4'b0100;

    // Combinational logic to assert the correct flag
    assign is_ADD   = (Opcode == OP_ADD);
    assign is_SUB   = (Opcode == OP_SUB);
    assign is_LOAD  = (Opcode == OP_LOAD);
    assign is_STORE = (Opcode == OP_STORE);
    assign is_NOP   = (Opcode == OP_NOP);
    
endmodule