docs: Wave D LME-20 failure ledger and decision gate - #101
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Mine the publishable 0/20 pin into an item-level histogram. 0/20 is not empty ingest (mean 24.45 hits). Gate: PR5 first, then PR3/PR4/PR9; defer PR6-PR8. No quality claim. Co-authored-by: Siddhant Singh <sdntsng@users.noreply.github.com>
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Honest Wave D remasure: local PR2 6/30 (24/24 READER_MISS, oracles supported). Fresh Mem0 12/30 (MH 7/10) on the same dataset SHA. Mem0 leads; no SOTA. PR6-PR8 stay deferred. Co-authored-by: Siddhant Singh <sdntsng@users.noreply.github.com>
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Summary
Wave D diagnosis after merging PR #100 into
devonly (24be5ab). The publishable LME-20 pin is still 0/20 integrity, not quality. This PR records an item-level failure ledger, a decision gate, and the honest LoCoMo/Mem0 remasure.A 100% SOTA guarantee is not possible. The real bar remains: beat a fresh Mem0 run on the same pinned harness while OpMem/marketing stay green. Today Mem0 leads that pin.
Changes
docs/benchmarks/artifacts/lme20-product-recall-pr1-20260812-failure-ledger.md— LME-20 item labels (sanitized).docs/research/program-execution-status.md— histogram, gate, PR6–PR8 deferral, PR10 measurement.docs/benchmarks/artifacts/locomo-pr2-dev-1x30-20260813.md— local PR2 remasure 6/30.docs/benchmarks/artifacts/failure-ledger/locomo-pr2-dev-1x30.jsonl— 24/24 READER_MISS, oracles supported.docs/benchmarks/artifacts/locomo-mem0-samepin-pr10-20260813.md— fresh Mem0 12/30 (MH 7/10).Headline from the publishable LME json (gitignored):
Decision gate: PR5 first (#102), then PR3 (#103), PR4 (#104), PR9 (#105). PR6–PR8 deferred — 1×30 WRONG items are reader misses with coverage supported, not missing edges.
Same-pin (this day)
24be5abLocal 6/30 is a dip vs staging post-cutover 15/30. Do not blend with Gate 0 18/30. LME-20 quality remains 0/20; LME-100 is not a quality run.
Test plan
Linear / tracking
Competitive program after #100. Wave 1 code: #102–#105.
Risk / follow-ups
devand remasure before any quality language.main.