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tatan432 / AES_ENCODER

Star

RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

digital rtl aes-128 synthesis aes-encryption digital-design verilog-project encription synopsys-vcs synopsys-dc ee4415

Updated Dec 11, 2020
Verilog

SimplHDL / simplhdl

Star

Simulation and implementation flow for hardware description languages

asic fpga simulation vhdl verilog vivado systemverilog implementation questasim quartus systemrdl cocotb synopsys-vcs

Updated Sep 17, 2026
Python

vb000 / vcs-slave-mode

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Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

verilog-simulator shared-object synopsys-vcs

Updated Mar 5, 2020
Makefile

cong2738 / May_team_project_I2C_SPI

Star

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs

Updated Jul 24, 2025
VHDL

Abdul99Aleem / Network_Telemetry_SoC

Star

RISC-V Network Telemetry & Secure Packet Monitoring SoC-RTL design, AXI/AHB-Lite interconnects, hardware AES-128, packet telemetry, and verification using Synopsys VCS/Verdi.

verilog-hdl risc-v verdi axi systemverilog-hdl amba vlsi-design rtl-design synopsys-vcs soc-design software-hardware-codesign veer-el2

Updated Oct 17, 2026
SystemVerilog

pocper / IC_Contest

Star

全國大學校院積體電路設計競賽實作練習

verilog synopsys-vcs synopsys-dc cadence-innovus ic-contest

Updated Apr 25, 2026
Verilog

SeanS4 / rv32im-out-of-order-processor

Star

32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.

rtl systemverilog computer-architecture risc-v microarchitecture verdi rv32im synopsys-vcs synopsys-dc out-of-order-execution register-renaming

Updated Aug 13, 2026
SystemVerilog

grandhisrivyshnavi-alt / SPI_Master_Core

Star

APB based SPI master protocol

digital linting verilog synthesis synopsys-vcs synopsys-dc

Updated Apr 13, 2026

Rakesh-2306 / Ultra-Lightweight-RISC-V-Architecture-for-Anomaly-Detection-in-Healthcare-Application

Star

Designed a lightweight 3-stage RISC-V processor for anomaly detection applications using Verilog, with RTL verification, synthesis, floorplanning, placement, CTS, routing, and STA using Synopsys VCS, Design Compiler, and ICC2.

routing tcl riscv verilog synthesis risc synopsys risc-v placement tcl-scripts verilog-project static-timing-analysis floorplanning verilog-code synopsys-vcs synopsys-dc synopsys-iccii clock-tree-synthesis

Updated Oct 21, 2025
Verilog

Dhanush30-DV / APB-SPI-UVM-Verification

Star

UVM verification of an APB-to-SPI master core: APB and SPI agents, virtual sequences for all 4 SPI modes, end-to-end scoreboard, SVA, 95.45% functional coverage

assertions uvm systemverilog-hdl synopsys-vcs functional-coverage amba-apb-spi