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Rohith-04/README.md

Hi, I'm Rohith

ECE student interested in computer architecture, digital design, and VLSI.

Currently focused on Network-on-Chip design, exploring how communication and interconnects shape modern computer systems.

I also work with RISC-V and SoC design as part of learning computer systems from the hardware up.

Blog

I write about what I build and learn, mostly around computer architecture, NoCs, digital design, and VLSI.

Read my blog →https://rohith-04.github.io

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  1. NoC NoC Public

    A reusable, synthesizable Network-on-Chip IP written in SystemVerilog for FPGA prototyping and future multicore SoC integration.

    SystemVerilog

  2. Honours_Project Honours_Project Public

    A near-data accelerator SoC built around the VeeR EL2 RISC-V core, with a custom AXI4 interconnect and UART/GPIO/Timer peripherals.

    SystemVerilog