pseudo-lru

Here are 4 public repositories matching this topic...

AmberVats / l1-cache-controller

32KB 4-Way Set-Associative L1 Cache Controller with Non-Blocking MSHR, Tree-PLRU, and AXI4 Refills targeting SkyWater 130nm.

asic systemverilog yosys axi4 cache-controller l1-cache mshr pseudo-lru skywater130

Updated Aug 19, 2026
SystemVerilog

KevinLaner15 / n-way-cache-controller

Star

Parameterized N-way set-associative write-back cache controller in Verilog, with selectable true LRU or tree pseudo-LRU replacement, a self-checking testbench, and hit-rate results.

fpga cache lru rtl verilog computer-architecture testbench lru-cache digital-design plru cache-controller pseudo-lru

Updated Oct 15, 2026
Verilog

sashakatne / Split-L1-Cache-simulator

Star

C++20 split L1 cache model (8-way data, 4-way instruction) with simplified MESI and pseudo-LRU; fixed an I-cache way-0 lookup bug, locked in with a 14-trace golden regression.

cpp cpu-cache computer-architecture cache-simulator memory-hierarchy mesi cache-coherence write-back pseudo-lru

Updated Sep 24, 2026
C++

Adam010341 / CompArch-cache-aware-riscv-optimization

Star

Tree-PLRU cache replacement in Spike + cache-blocked matrix transpose (-76% misses) + RVV-tiled GEMM for MLP inference.

cache spike riscv cache-simulator gemm loop-tiling rvv pseudo-lru

Updated Oct 3, 2026
C

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