3rd-year Electrical Engineering student at Queen's University (BASc, graduating 2028). I like building things that sit between hardware and software including PCBs, embedded systems, and digital design.
- Learning Verilog and digital design (RTL, FSMs, timing)
- Applying it to hardware projects like my cache controller, and looking for more to build
- Leading the power systems subteam for Queen's VEX U Robotics
- Looking for a 12 or 16 month co-op starting May 2027 in electrical / hardware / digital design
Parameterized N-way set-associative, write-back, write-allocate cache controller in Verilog. The replacement policy is selectable between true LRU and tree pseudo-LRU. A self-checking testbench compares every read against a reference model across directed, random, and hot/cold access tests. Repo
Buck converter redesign and battery system optimization. Designed a USB-C to barrel jack adapter, a 5V to 3.3V LDO regulator, reverse polarity protection, and an I2C power monitor for battery level.
Designed the power management PCB for a low-cost handheld neonatal jaundice sensor.
Languages: Verilog, VHDL, C, C++, Assembly, Python, MATLAB
Tools: ModelSim, Quartus, KiCad, LTspice, ETAP, AutoCAD, AGi32, Fusion 360, SolidWorks
Electrical Engineering Intern at Greer Galloway (Jp2g Consultants), Summers 2025 and 2026. Electrical building services design, load calculations, lighting analyses, and standardized ETAP models.