nangate45

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Here are 8 public repositories matching this topic...

karder1 / openroad-gcd-rtl-to-gds

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RTL-to-GDSII physical design flow for the GCD design using OpenROAD-flow-scripts and Nangate45.

asic vlsi operand yosys nan physical-design opensta rtl-to-gds nangate45

Updated Jul 18, 2026
Verilog

karder1 / openroad-alu-rtl-to-gds

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8-bit ALU RTL-to-GDSII physical design using OpenROAD-flow-scripts and Nangate45.

asic verilog alu gtkwave vlsi yosys physical-design openroad opensta rtl-to-gds nangate45

Updated Jul 22, 2026
Verilog

jawadsa02 / qos-scheduler-timing-rescue

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Timing and congestion rescue for a QoS scheduler — one-variable experiments, conditional RTL escalation

timing eda orfs physical-design openroad nangate45

Updated Aug 26, 2026
Verilog

karder1 / openroad-counter-rtl-to-gds

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8-bit counter RTL-to-GDSII physical design using OpenROAD-flow-scripts and Nangate45.

asic verilog gtkwave vlsi yosys physical-design openroad opensta rtl-to-gds nangate45

Updated Jul 20, 2026
Tcl

jawadsa02 / qos-scheduler-rtl2gds

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RTL-to-GDSII baseline for a QoS egress scheduler — OpenROAD/ORFS on Nangate45

eda orfs physical-design openroad rtl2gds nangate45

Updated Aug 26, 2026
Verilog

ShahabuddinDanish / iir-filter-vlsi

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Full VLSI design flow for a 1st-order IIR low-pass filter. It includes VHDL RTL, fixed-point C model, Synopsys DC synthesis with clock gating, and Cadence Innovus place & route. The advanced architecture of the filter applies J-look-ahead, pipelining, and retiming to achieve 581 MHz, a 47% throughput gain over the standard architecture.

Updated May 4, 2026
VHDL

amoghpaduvani / liberty-timing-analyzer

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Parser and interactive visualizer for Liberty (.lib) STA timing files — verified across Sky130, NanGate45, GF180MCU, and IHP SG13G2

python eda liberty vlsi sta timing-analysis streamlit sky130 gf180mcu nangate45

Updated Jul 23, 2026
Python

jawadsa02 / qos-scheduler-signoff

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PDN inspection, PDNSim, and signoff handoff for a QoS scheduler — repeatable release Tcl

eda orfs signoff physical-design openroad nangate45

Updated Aug 26, 2026
Verilog

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