FPGA-based Sobel Filter Edge Detection
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Updated
Jul 13, 2025 - Verilog
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line-buffer
Here are 3 public repositories matching this topic...
VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.
mux comparator seven-segment traffic-light-controller chip-design digtial-design adder-circuit line-buffer ring-counter four-digit-seven-segment-driver
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May 30, 2022 - VHDL
Streaming N-by-N CNN convolution accelerator on Xilinx Zynq-7020 – 50 LUT / 9 DSP / 0 BRAM / 464 MHz at 2.155 ns / FOM 0.01550 – IEEE SSCS Egypt 2026 Student Design Competition (Team FlipFlopers, Cairo University)
fpga rtl verilog vivado fixed-point modelsim cnn-accelerator edge-ai zynq-7020 line-buffer dsp48e1 ieee-sscs
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Sep 25, 2026 - Verilog
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