Silicon workbench for chip blueprints, roofline analysis, tile-memory flow, and AI accelerator co-design.
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Updated
Oct 9, 2026 - HTML
Silicon workbench for chip blueprints, roofline analysis, tile-memory flow, and AI accelerator co-design.
Reproducible study of how tensor layout, reduction length, and pointer alignment drive vendor GEMM dispatch and latency cliffs.
Custom GPT-2 GPU inference engine with fused Triton kernels, KV-cache, and INT8 quantization. Hand-crafted & verified to FP32 correctness.
Diagnosing non-monotonic activation memory in torch.compile's memory-budget partitioner, with a use-site rematerialization fix.
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