Design Verification Engineer focused on digital systems, hardware verification, and performance-oriented engineering tools.
I work across RTL verification, SystemVerilog, UVM, simulation, and hardware–software co-design. I value disciplined engineering, clear technical communication, and solutions that can be tested, measured, and improved.
A silicon workbench for chip blueprints, roofline analysis, tile-memory flow, and AI accelerator co-design. TileLens combines hardware profiles, workload modeling, memory analysis, and interactive visualization to study performance trade-offs across modern processors and accelerators.
Parameterized synchronous FIFO implemented in SystemVerilog and verified through progressive directed, layered, and UVM environments. The project covers configurable FIFO depth and data width, pointer wrapping, simultaneous read/write behavior, overflow and underflow handling, scoreboarding, constrained-random stimulus, and regression testing.
- SystemVerilog and RTL design
- UVM testbench architecture
- Constrained-random verification and functional coverage
- Assertions, protocol checking, and simulation debug
- Hardware performance modeling and memory systems
- Python, scripting, and engineering automation
For professional opportunities, engineering collaborations, or technical discussions, connect through my portfolio or GitHub.