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dmaengine: qcom: gpi: order event ring pointer reads - #45

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dmaengine: qcom: gpi: order event ring pointer reads#45
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@ooaklee

@ooaklee ooaklee commented Sep 3, 2026

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Summary

Use ordered MMIO reads for the GPI event-ring read pointer before consuming
events written by the device into coherent memory.

This is a one-variable replacement for the withdrawn early-EOT experiment in
#42. It does not change QSPI completion policy, descriptor ownership, SPI HID,
the MSHW0485 driver, recovery, runtime PM, or userspace.

Evidence boundary

Proven from the failed beta boots:

  • beta2 and v6 repeatedly accepted a QSPI RX completion with descriptor length
    3628 and reported residue 3628, so the event length was observed as zero;
  • v19 on the same Surface Pro 11 has not produced that pair failure;
  • v7's additional early-completion path turned the existing failure into an
    invalid-cookie kernel BUG, so that patch and its aggregate were withdrawn.

The missing read-side ordering is a hypothesis, not yet a hardware-qualified
root cause. The GPI driver reads the device producer pointer with
readl_relaxed() and immediately reads dma_alloc_coherent() event memory.
Linux's MMIO contract reserves ordered readl() for exactly this relationship.
The analogous Qualcomm IPA GSI event-ring path also uses ordered ioread32().

Scope and guardrail

  • only gpi_read_ev_rp() changes;
  • all unrelated register accesses remain relaxed;
  • the shared helper covers both gpi_process_events() and
    gpi_mark_stale_events();
  • both halves of Denali's retained 64-bit pointer are read with the same ordered
    accessor;
  • no module parameter, timing delay, logging dependency, zero-length-event
    suppression, or cookie workaround is introduced.

The change is generic because ordering a device publication pointer before its
coherent payload is a GPI core correctness requirement, not Denali hardware
policy. SP11 qualification can validate the exposed QSPI case; wider upstream
submission will still require review and regression coverage on other GPI
clients.

Validation

  • git diff --check: pass
  • strict patch checkpatch.pl: 0 errors, 0 warnings, 0 checks
  • ARM64 drivers/dma/qcom/gpi.o build using the v7 configuration: pass
  • two adversarial OpenCode passes: no critical, high, or medium findings after
    correcting the MMIO/DMA and split-pointer analysis

Hardware qualification

Keep this PR draft and unmerged until a touch-only beta build passes on the
Surface Pro 11 with tracing disabled:

  1. cold boot and confirm the expected DTB and ABI;
  2. sustain touchscreen and pen use well beyond the former three-second failure;
  3. repeat suspend/resume and HIDRAW recovery;
  4. verify no SP11 QSPI pair failed, zero-length completion, DMA cookie BUG,
    host-fault loop, or loss of the IPTS bridge;
  5. soak long enough to exercise repeated transfers without diagnostic timing
    overhead.

Failure with the same residue signature falsifies this hypothesis and this PR
must be closed rather than expanded in place.

Merge policy

Do not merge on compile evidence alone. Do not combine this test with the
speaker repair or any other unqualified topic.

@ooaklee

ooaklee commented Sep 3, 2026

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Qualification bundle is ready in draft PR #46.

  • exact source revision: 8fbab0760dca728ccedcd9e9eb9de2a314ea4851
  • source tree: 04d9ec207dcbd8a33aa6803249917495fcaf3e00
  • isolated Lexr --reset-source build: pass
  • ABI: 7.2.2-jg-0sp11v8-qcom-x1e
  • packages: four; all SHA256SUMS entries pass
  • Lexr kernel inspect --json: pass
  • modules package contains gpi.ko.zst and both declared Surface DTBs

The full Ubuntu configuration emitted five non-fatal warnings in unrelated,
unmodified UCSI, Mellanox, and WireGuard code. No warning involved GPI, SPI,
HID, IPTS, device tree, or packaging.

PR #46 records the controlled hardware protocol. Because software mute did not
contain the failed v7 audio static, the first v8 boot will transiently blacklist
the X1E machine/SoundWire modules through a one-time GRUB edit. A pass therefore
qualifies touch transport under audio isolation only and remains merely
consistent with the ordering hypothesis; it is not final combined-beta
qualification.

Keep this PR draft and unmerged until the physical gates in #46 pass.

@ooaklee

ooaklee commented Sep 3, 2026

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Message-only submission cleanup

The commit message was wrapped to satisfy full-patch checkpatch.pl; source tree 151890649ef2faa531f087e76e06afadb7b23a2a, author identity, and author date are unchanged. Current head: f35a9f804bdf3666820737d1a4d0df7bd1b82249. Full patch and per-commit source checks now pass with zero findings.

The device writes event elements into coherent memory before publishing
its event ring read pointer. Both gpi_process_events() and
gpi_mark_stale_events() read that pointer through readl_relaxed() and then
consume the event memory without an ordering guarantee.

On architectures such as arm64, this can expose a published event before
all its fields are visible. Denali QSPI exposed this as an accepted
completion whose length was observed as zero.

Use ordered MMIO reads only for the event pointer. Keep all other register
accesses relaxed. This follows the ordered ioread32() pattern used by the
Qualcomm IPA GSI event-ring consumer.

Fixes: 5d0c353 ("dmaengine: qcom: Add GPI dma driver")
Signed-off-by: Leon Silcott <leon@boasi.io>
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