Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 5 additions & 2 deletions .github/workflows/cicd.yml
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,9 @@ name: "Lint, simulate, synthesize, test and docs"

on: [push]

env:
SPEED: ${{ github.ref == 'refs/heads/main' && 'full' || 'simfast' }}

jobs:
lint:
name: "Run pre-commit lint"
Expand Down Expand Up @@ -42,7 +45,7 @@ jobs:
with:
fetch-depth: 0
- name: Simulation
run: make sim
run: make sim SIM_SPEED=${{ env.SPEED }}
- name: Upload
uses: actions/upload-artifact@v7
with:
Expand All @@ -68,7 +71,7 @@ jobs:
with:
fetch-depth: 0
- name: Synthesis
run: make synth
run: make synth SYNTH_SPEED=${{ env.SPEED }}
- name: Upload
uses: actions/upload-artifact@v7
with:
Expand Down
10 changes: 8 additions & 2 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -8,16 +8,22 @@
BUILD_DIR := build
CACHE_DIR := .cache

# Can be default, simfast, full, minimal
SIM_SPEED ?= simfast

# Can be default, simfast, full, minimal
SYNTH_SPEED ?= simfast

# Default target
all: lint test synth sim

# Run Verilator RTL test benches
sim:
uv run pytest python/tb -m sim --speed simfast
uv run pytest python/tb -m sim --speed $(SIM_SPEED)

# Run Yosys synthesis and generate utilization reports
synth:
uv run pytest python/tb -m synth --speed simfast
uv run pytest python/tb -m synth --speed $(SYNTH_SPEED)

# Run Python tests
test:
Expand Down
1 change: 1 addition & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ The Mini-ISP philosophy is summarized as follows:
- Acceptable image quality: Image quality must be acceptable for most applications and subjectively pleasant to the human eye.
- Open-source: All code and test cases are publicly available under a permissive license.

For more information and resource usage statistics, please refer to [the documentation](https://amd.github.io/mini-isp).

## Table of Contents

Expand Down
13 changes: 13 additions & 0 deletions rtl/ccm.sv
Original file line number Diff line number Diff line change
Expand Up @@ -489,6 +489,19 @@ module ccm

if (rstn == 1'b0) begin
pipe_2_tvalid <= '0;
// Reset the accumulator registers. Should not be required, but Yosys optimizes away the DSPs without reset.
Comment thread
timor-amd marked this conversation as resolved.
pipe_2_pixel0_r <= '0;
pipe_2_pixel0_g <= '0;
pipe_2_pixel0_b <= '0;
pipe_2_pixel1_r <= '0;
pipe_2_pixel1_g <= '0;
pipe_2_pixel1_b <= '0;
pipe_2_pixel2_r <= '0;
pipe_2_pixel2_g <= '0;
pipe_2_pixel2_b <= '0;
pipe_2_pixel3_r <= '0;
pipe_2_pixel3_g <= '0;
pipe_2_pixel3_b <= '0;
end
end

Expand Down