Feature/ccm resource fix

[timor-amd]

Yosys needs some pipe pixel to be reset in order to correctly infer the CCM DSPs.

Also, added full synthesis and simulation runs when merging to main, so that full resource usage statistics are available when the docs are main generated. Also added another link to the documentation in README.

[Copilot]

Pull request overview

This PR addresses a Yosys inference issue by adding explicit resets in the CCM pipeline so DSP blocks are not optimized away, and updates the build/CI flow to run “full” simulation and synthesis on main to produce complete resource-usage artifacts for published documentation.

Changes:

• Reset CCM stage-2 pixel accumulator registers during reset to preserve DSP inference in Yosys.
• Add SIM_SPEED / SYNTH_SPEED Makefile parameters and wire them through CI, using full on main and simfast otherwise.
• Add a README link pointing users to the hosted documentation (including resource usage stats).

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 1 comment.

File	Description
rtl/ccm.sv	Adds reset assignments for stage-2 pixel accumulator registers to prevent Yosys from optimizing away DSP inference.
README.md	Adds a documentation link for resource usage statistics.
Makefile	Introduces SIM_SPEED / SYNTH_SPEED variables and uses them for sim/synth targets.
.github/workflows/cicd.yml	Sets speed based on branch and passes it to make sim / make synth so main runs full flows.

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