gt2n: add 2nm BSPDN platform with gcd and aes designs

.gitignore

@@ -63,6 +63,7 @@ flow/platforms/*
 !flow/platforms/sky130io
 !flow/platforms/sky130ram
 !flow/platforms/gf180
+!flow/platforms/gt2n
 flow/private
 
 # network

flow/designs/gt2n/aes/config.mk

@@ -0,0 +1,19 @@
+export DESIGN_NICKNAME = aes
+export DESIGN_NAME     = aes_cipher_top
+export PLATFORM        = gt2n
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+# AES is bigger than gcd; give the floorplan more room.
+export CORE_UTILIZATION       = 30
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY_LB_ADDON = 0.20
+
+export TNS_END_PERCENT = 100
+# workaround for high congestion in post-grt repair (matches nangate45/aes)
+export SKIP_INCREMENTAL_REPAIR = 1
+
+export SWAP_ARITH_OPERATORS = 1
+export OPENROAD_HIERARCHICAL = 1

flow/designs/gt2n/aes/constraint.sdc

@@ -0,0 +1,17 @@
+current_design aes_cipher_top
+
+set clk_name clk
+set clk_port_name clk
+# GT2N lib uses time_unit = 1 ps. 500 ps -> 2 GHz target; first-pass
+# loose, can tighten once routing is clean.
+set clk_period 500
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/gt2n/gcd/config.mk

@@ -0,0 +1,11 @@
+export DESIGN_NICKNAME = gcd
+export DESIGN_NAME     = gcd
+export PLATFORM        = gt2n
+
+export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
+
+export CORE_UTILIZATION   = 25
+export CORE_MARGIN        = 0.5
+export PLACE_DENSITY      = 0.35
+export TNS_END_PERCENT    = 100

flow/designs/gt2n/gcd/constraint.sdc

@@ -0,0 +1,17 @@
+current_design gcd
+
+set clk_name core_clock
+set clk_port_name clk
+# 500 ps clock (2 GHz) — modest target; lib path delays grow once realistic
+# wire RC kicks in. Tighten once a clean run lands.
+set clk_period 500
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/platforms/gt2n/LICENSE

@@ -0,0 +1,28 @@
+BSD 3-Clause License
+
+Copyright (c) 2025, azadnaeemi
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

flow/platforms/gt2n/README.md

@@ -0,0 +1,58 @@
+# GT2N PDK
+
+> **Source:** copied verbatim from [azadnaeemi/GT2N](https://github.com/azadnaeemi/GT2N) at commit [`54f81feb2b`](https://github.com/azadnaeemi/GT2N/commit/54f81feb2b9c334d283538c1bc91bf3a34b02c02) (2026-06-05). This release split the original `gt2_6t_tap_w31_lvt` into a frontside-PDN variant (`gt2_6t_tapfspdn_w31_lvt`) and a backside-PDN variant (`gt2_6t_tapbspdn_w31_lvt`); the latter is what this ORFS platform points `TAP_CELL_NAME` at, since the PDN here is backside-only. Resolves the original BPR `OBS` → `PORT` issue ([azadnaeemi/GT2N#12](https://github.com/azadnaeemi/GT2N/issues/12)).
+
+<img src="./VirtualFabricationDemo.gif" alt="VirtualFabricationDemo" width="400">
+
+This is the initial release for the GT2N PDK with 71 standard cells. It is based on 2nm GAAFET with BSPDN.
+
+If you use this PDK for publishing your work, we would appreciate citation of the following paper:
+
+D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking," in IEEE International Symposium on Circuits and Systems (ISCAS) 2026 [link](https://www.dropbox.com/scl/fi/3to35aip31hfqj76q7g5x/dongwon_iscas26.pdf?rlkey=utm8my3qq36y8mo0hkvto6tnv&st=876o2oh8&dl=0).
+
+Quick setup guide for Custom Compiler:
+
+Create a folder (e.g. gt2_techlib) and copy GT2N/techlib/nmos_lvt and GT2N/techlib/pmos_lvt inside that folder.
+Inside the folder from where custom_compiler is run, add the following to the lib.defs file:
+gt2_official <path_to_techlib_directory>/gt2_techlib
+
+You can specify any name for the library instead of using gt2_offical. The current standard cell schematics are linked with the devices using this name. In case any other library name is used, the device references might need to be updated in the schematics.
+
+To assign technology to the lib, the following .tf file can be imported using "Technology Manager" and applied to the gt2_official lib:
+GT2N/techlib/gt2_techfile.tf
+
+To import all the standard cells, either custom_compiler .oa format or .gds files can be used.
+Create a folder for the standard cell library (e.g. gt2_std_cells) and add it to the lib.defs file:
+gt2_std_cells <path_to_std_cells_directory>/gt2_std_cells
+
+In the "Technology Manager", the associated technology needs to be changed to gt2_official (or the lib name used in the previous stage). Alternatively, the .tf file can also be imported and applied to gt2_std_cells. This is necessary, otherwise layers would not be identified. Any new library created needs to follow the same process. To assign colors to the layer, load "GT2N/techlib/gt2_layer_colors.tcl" using the "Display Resource Manager".
+
+Copy everything inside GT2N/std_cells folder to gt2_std_cells. This includes layouts, schematics, and abstract views for custom_compiler.
+
+Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gds
+
+LVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
+
+Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)
+
+The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):
+
+LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
+
+LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
+
+Techlef: GT2N/techlib/gt2_tech.lef
+
+ICT: GT2N/qrc/GT2.ict
+
+QRCTech: GT2N/qrc/GT2_qrc.tch
+
+ITF: GT2N/nxtgrd/GT2.itf
+
+NXTGRD: GT2N/nxtgrd/GT2.nxtgrd
+
+The GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):
+
+GT2N/device/tt/gt2_w31_lvt_tt.sp
+
+BSPDN support for Cadence Innovus implementation flow is under development.

flow/platforms/gt2n/cells_clkgate.v

@@ -0,0 +1,7 @@
+// GT2N has no clock gate cell; provide a passthrough that Yosys can target.
+module OPENROAD_CLKGATE (CK, E, GCK);
+  input CK;
+  input E;
+  output GCK;
+  assign GCK = CK;
+endmodule

flow/platforms/gt2n/config.mk

@@ -0,0 +1,85 @@
+# GT2N PDK platform - 2nm GAAFET with BSPDN (backside power)
+# Uses w31 LVT cells at the tt 0.7V/25C corner. Collateral lives entirely
+# under this platform dir.
+
+export PROCESS = 2
+
+#-----------------------------------------------------
+# Tech/Libs
+#-----------------------------------------------------
+export TECH_LEF = $(PLATFORM_DIR)/lef/gt2_tech.lef
+export SC_LEF   = $(PLATFORM_DIR)/lef/gt2_6t_w31_lvt.lef
+
+export LIB_FILES = $(PLATFORM_DIR)/lib/gt2_6t_w31_lvt_tt_0p7v25c.lib \
+                   $(ADDITIONAL_LIBS)
+export GDS_FILES = $(PLATFORM_DIR)/gds/gt2_6t_std_cells_w31_lvt.gds \
+                   $(ADDITIONAL_GDS)
+
+# Cells that should not be used in synthesis/optimization
+export DONT_USE_CELLS = gt2_6t_filler_w31_lvt gt2_6t_tapbspdn_w31_lvt \
+                       gt2_6t_tapfspdn_w31_lvt gt2_6t_decapcc_w31_lvt \
+                       gt2_6t_tiehigh_w31_lvt gt2_6t_tielow_w31_lvt
+
+# Fill cells used in fill cell insertion
+export FILL_CELLS ?= gt2_6t_filler_w31_lvt gt2_6t_decapcc_w31_lvt
+
+#-----------------------------------------------------
+# Yosys / synthesis
+#-----------------------------------------------------
+export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
+
+export TIEHI_CELL_AND_PORT = gt2_6t_tiehigh_w31_lvt Y
+export TIELO_CELL_AND_PORT = gt2_6t_tielow_w31_lvt  Y
+
+export MIN_BUF_CELL_AND_PORTS = gt2_6t_buf_x1_w31_lvt A Y
+
+# No latch/adder cells in this library; skip those map files
+export LATCH_MAP_FILE   =
+export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v
+export ADDER_MAP_FILE   =
+
+export ABC_DRIVER_CELL = gt2_6t_buf_x1_w31_lvt
+# Cap value derived from inv_x1 input cap (~0.5 fF). Multiply by 4.
+export ABC_LOAD_IN_FF = 2.0
+
+#--------------------------------------------------------
+# Floorplan
+#--------------------------------------------------------
+export PLACE_SITE = gt2_6t
+
+# IO pin placement layers
+export IO_PLACER_H ?= M2
+export IO_PLACER_V ?= M3
+
+# Define default PDN config
+export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl
+
+# Endcap and Welltie cells
+export TAPCELL_TCL ?= $(PLATFORM_DIR)/tapcell.tcl
+export TAP_CELL_NAME = gt2_6t_tapbspdn_w31_lvt
+
+export MACRO_PLACE_HALO ?= 1.0 1.0
+
+#---------------------------------------------------------
+# Place
+#---------------------------------------------------------
+export PLACE_DENSITY ?= 0.40
+
+#---------------------------------------------------------
+# Route
+#---------------------------------------------------------
+export MIN_ROUTING_LAYER = M2
+export MIN_CLK_ROUTING_LAYER = M3
+export MAX_ROUTING_LAYER = M5
+
+export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl
+
+# KLayout technology file (drives GDS export)
+export KLAYOUT_TECH_FILE = $(PLATFORM_DIR)/gt2.lyt
+
+#---------------------------------------------------------
+# IR Drop
+#---------------------------------------------------------
+export PWR_NETS_VOLTAGES ?= vdd 0.7
+export GND_NETS_VOLTAGES ?= vss 0.0
+export IR_DROP_LAYER ?= BPR

flow/platforms/gt2n/fastroute.tcl

@@ -0,0 +1,5 @@
+set_global_routing_layer_adjustment M2-M3 0.5
+set_global_routing_layer_adjustment M4-$::env(MAX_ROUTING_LAYER) 0.25
+
+set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
+set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)