gt2n: add 2nm BSPDN platform with gcd and aes designs#4277
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This pull request introduces support for the GT2N PDK platform, a 2nm GAAFET technology with backside power distribution. It adds configuration and constraint files for the AES and GCD designs, platform-specific files (including LEF, layer maps, KLayout technology, PDN, and RC scripts), and updates the OpenROAD and Yosys submodules. The review feedback highlights minor typos in the README documentation and points out an inconsistency in the backside metal label layer mapping within the KLayout technology file (gt2.lyt).
mguthaus
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Very interesting! We're using asap7 today, is this something that is worth looking at now or is it too early? Can you say something to manage my expectations w.r.t. using this as a drop-in replacement for asap7? Wiring this up to bazel-orfs (which I use) should be easy enough. |
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With only 71 std cells it isn't a very rich library. |
I see. asap7 can't do Kogge Stone because half adder variants aren't available, so buffers are used instead defeating the Kogge Stone optimization. |
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There is one size of half-adder HAxp5_ASAP7_75t_R, do you mean the lack of size variants? |
Yes: so you get lots of buffers, which eats into the Kogge Stone advantage, which means that all those adder carry chain propagation tricks cluster around the same performance in graphs... Vt mitigates this a bit in a sense. |
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@mguthaus You've played around with bazel-orfs, I had Claude create idiomatic support in GT2N azadnaeemi/GT2N#13 |
Brings up the GT2N 2nm GAAFET PDK with buried-power-rail (BSPDN) and
runs gcd through it end-to-end with the OpenROAD changes on the
bspdn branch of tools/OpenROAD.
* flow/platforms/gt2n/ new platform:
config.mk top-level platform variables.
fastroute.tcl, pdn.tcl, setRC.tcl, tapcell.tcl, cells_clkgate.v
ORFS step config; PDN is BPR followpins
only (backside rails come from elsewhere).
lef/, lib/, gds/ copy of the GT2N tt w31 LVT collateral.
gt2.lyt, gt2.lyp KLayout tech + per-layer colors (rainbow
for front-side M0..M13 + RDL, warm/red
shades for backside BPR/BM*/BRDL).
gt2.layermap LEF layer -> GDS layer mapping.
LICENSE, README.md upstream attribution.
The local copy of gt2_6t_w31_lvt.lef carries a small authoring fix
on the gt2_6t_tap_w31_lvt cell: BPR shapes that were declared as
OBS are moved into a second PORT on each PG pin so the LEF
correctly encodes the M1<->BPR bridge. Suggested upstream as
azadnaeemi/GT2N#12.
* flow/designs/gt2n/gcd/ new design:
config.mk, constraint.sdc
* tools/OpenROAD bump to bspdn tip (0e7eabb59d) which adds
isBackside()/LEF58_BACKSIDE support and
filters backside layers out of DRT.
* tools/yosys pin to v0.64 release (6d2c445a) which
works around the Ubuntu 24.04 / glibc 2.39
yosys-abc pipe deadlock in newer SHAs.
* .gitignore whitelist flow/platforms/gt2n.
Verified: gt2n/gcd produces 6_final.{def,gds,odb,sdc,v}.
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
BPR followpins on their own do not stitch the per-row vdd/vss rails together, so the backside grid was a chain of disconnected horizontal strips. Add a two-layer perpendicular mesh (BM1 vertical, BM2 horizontal) plus BV0/BV1 connects, modeled on asap7's M5/M6 over M1/M2 followpin pattern. Top of the standard-cell grid is now BM2. Also adds resistance values for the backside cut layers (BV0..BV4) to setRC.tcl so PSM's analyze_power_grid does not error out with PSM-0021 when the PG network includes backside vias. Calls out that every RC value in this file is a placeholder, not silicon-calibrated. Verified end-to-end on gt2n/gcd: 873s wall time, 0 DRC violations, 0 ANT violations. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Picks up the merged LEF58_BACKSIDE / BSPDN support (PR #10547, merge commit e03cf07c) plus 5 unrelated post-merge upstream commits (ord boost exe-find, gui power density heatmap, odb inst-to-chip-bump, bazel runfiles, gadfort fix-bazel). Supersedes the interim development pins (df6deec2ca, b6bf791a86) which pointed at the VLSIDA fork during PR review. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
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@maliberty @oharboe You are correct that it is a functionally small library. One dimension that I did not include are the 10 different VTh variants in the library. While there aren't that many sizes, FinFETs are better off using VTh instead of multiple discrete fins. This would increase the commit by ~1MB+ to include those files, so I opted to just do the baseline. Should I add this? |
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@mguthaus Perhaps you could try out my PR? If it is accepted, we could expand it to use everything in the gt2n repo without worrying about size, it is all there already, I suppose. |
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Adds the GT2N 2 nm GAAFET PDK to ORFS as a new platform, with two reference designs (
gcd,aes) routed end-to-end.GT2N is an open-source process-aware 2 nm nanosheet PDK developed at Georgia Tech / Synopsys / Samsung (Jang et al., IEEE APCCAS 2024, https://github.com/azadnaeemi/GT2N). The collateral here is the
tt 0.7 V 25 Ccorner of the W31 LVT 6T library, used unchanged except for one authoring fix on the tap cell (gt2_6t_tap_w31_lvt): BPR shapes that were declared asOBSare moved into a secondPORTon each PG pin so the LEF correctly encodes the M1↔BPR bridge (suggested upstream asazadnaeemi/GT2N#12).What's in the PR
flow/platforms/gt2n/— config, LEF/Lib/GDS, KLayout.lyp/.lyt,.layermap, PDN/RC/tapcell scripts, LICENSE/README.flow/designs/gt2n/gcd/,flow/designs/gt2n/aes/— config + SDC.tools/OpenROAD→a44e99193f(= upstream master HEAD, includes the merged LEF58_BACKSIDE / BSPDN support from The-OpenROAD-Project/OpenROAD#10547).Platform architecture
BSPDN-style: every standard cell's
vdd/vsspin lives onBPR(backside, markedLEF58_BACKSIDE). The PDN is therefore backside-only:BPRfollowpins (pitch 144 nm) sit directly under each row, overlapping the cell's BPR pin → power gets to the device through the cell's intrinsic nano-TSV / WAC structure modelled in the PDK (per Jang et al. §II.A).BM1mesh perpendicular to BPR, connected viaadd_pdn_connect BPR BM1.BM2mesh perpendicular to BM1, declared as the grid's top pin, connected viaadd_pdn_connect BM1 BM2.All three
add_pdn_connectrules are backside-only by design; the PDN-1200 cross-side guard added in OpenROAD#10547 stays silent. There are no chip-level TSVs or bridge cells in this configuration — that's intentional, matching the paper's architecture.Signal routing is the frontside stack
M2..M5(MIN_ROUTING_LAYER/MAX_ROUTING_LAYER); frontside metals aboveM5and the entire backside stack are excluded from signal routing.Verification
make … 5_2_routeclean (13 min wall, 2.2 GB peak, 0 violations, 0 antenna violations).make … 5_2_routeclean (1 h 39 min wall, 10.7 GB peak, 0 violations).make … 2_4_floorplan_pdnongcdruns clean (2 s, BPR followpins + BM1/BM2 mesh inserted by PDN without warnings).Notes
.liband 4 802-line.lefare the upstream GT2N library payload, not authored here. Licensing matches the upstream (BSD-style; seeflow/platforms/gt2n/LICENSE).setRC.tcluses placeholder values for the backside layers and vias — the upstream PDK does not ship extracted backside RC. The values are scaled like the frontside (V0..V4) so timing isn't pathologically off.gcdandaes.