Sanjay SanjayG-xls

`whoami`

🎓 B.E. Electronics Engineering — VLSI Design & Technology
🏛️ Chennai Institute of Technology (CIT) 2025 – 2029

🔬 Core Domain

⚡ Also Focused On

"I don't just write code — I architect silicon."

🔬 VLSI Design Flow — My Playground

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flowchart LR
    A["📝 RTL\nVerilog"] -->|Synthesize| B["⚙️ Synthesis\nNetlist Gen"]
    B -->|Constraints| C["📐 Floorplan\nPlace"]
    C -->|Optimize| D["🕐 CTS\nClock Tree"]
    D -->|Connect| E["🔀 Route\nInterconnect"]
    E -->|Verify| F["📊 STA\nSign-off"]
    F -->|Check| G["✅ DRC\nLVS"]
    G -->|Export| H["💎 GDSII\nTapeout"]
    H -->|Fabricate| I["🔬 SILICON\nWafer"]

    style A fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style B fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style C fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style D fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style E fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style F fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style G fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style H fill:#238636,stroke:#7ee787,stroke-width:3px
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⚙️ EDA & Semiconductor Toolchain

🧪 VLSI EDA & Circuit Simulation

_Virtuoso _{Schematic · Layout}	_Verdi _{Debug · Waveform}	_Ngspice _{SPICE Simulation}	_LTspice _{Analog Sim}
_eSim _{Mixed Signal}	_KiCad _{PCB Design}	_EasyEDA _{Schematic · PCB}	_SCS _Spectre

🧬 HDL & Verification

_{Verilog HDL}
_{RTL Design · Testbench} _{SPICE Netlists}
_{Circuit Simulation} _{RTL Verification}
_{Functional · Timing}

🛠️ Embedded Systems · IoT · Hardware

_STM32F4VE _{ARM Cortex-M4}	_NXP _{MCU Platforms}	_{Raspberry Pi} _{SBC · Edge Node}	_Arduino _{Uno · Nano}
_{Custom PCB} _{Schematic → Layout}	_{ARM Cortex} _Architecture	_{IoT Systems} _{Ultra-Low-Power}	_{Sensors & Actuators} _Interfacing

🧠 Deep Learning · Edge AI · Computer Vision

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flowchart TD
    A["🖥️ Train on GPU"] --> B["🧠 CNN\nResNet"]
    A --> C["👁️ YOLO\nReal-time Detection"]
    A --> D["🔗 Siamese MobileNet\nSimilarity Matching"]
    B --> E["📦 Quantize & Optimize"]
    C --> E
    D --> E
    E --> F["🔬 Deploy to Edge"]
    F --> G["STM32"]
    F --> H["Raspberry Pi"]
    F --> I["Edge TPU"]

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    style E fill:#0b3d0b,stroke:#7ee787,stroke-width:2px
    style F fill:#238636,stroke:#7ee787,stroke-width:3px
    style G fill:#0b3d0b,stroke:#58a6ff,stroke-width:2px
    style H fill:#0b3d0b,stroke:#58a6ff,stroke-width:2px
    style I fill:#0b3d0b,stroke:#58a6ff,stroke-width:2px

_TensorFlow
_{CNN Training} _PyTorch
_{Model Dev} _YOLO
_{Object Detection} _ResNet
_{Image Recognition} _{Siamese MobileNet}
_Similarity

⚡ Flagship Projects

🔬 AC/DC Converter Migration — 0.18µm CMOS Technology

📋 For: FOSSEE, IIT Bombay

🧪 Node: 0.18µm CMOS 🔧 Tools: eSim · Ngspice 📊 Scope: Functional Verification · Performance Analysis 🎯 Domain: Research-Level Power Electronics

Migrated a full AC/DC converter design into the eSim open-source EDA environment
Executed comprehensive functional verification and performance analysis via Ngspice
Validated against research-level power electronics specifications

🏗️ ACTOS — Automated Construction Tool Orchestration System

🔒 Status: Patent Pending

🌐 Architecture: Distributed IoT Ecosystem ⚡ Power: Ultra-Low-Power 🏭 Domain: Industrial Asset Management 📡 Stack: Sensor Nodes → Edge Gateway → Cloud Orchestration

Co-developing a distributed, ultra-low-power IoT ecosystem for industrial asset management
Embedded MCU nodes with sensor fusion feeding into edge processing and cloud orchestration
Patent pending — currently in active co-development

💼 Experience & Training

🏢 Ennovi Mobility Solutions — Intern, Electronic Systems

Analyzed mobility & electrification solutions with AI-integrated electronics. Collaborated with automation engineers on layout verification. Hands-on with electronic sensors, actuators, and Linux-based systems.

🎓 ASIC Design Training — NIELIT (National Institute of Electronics & IT)

Completed intensive RTL to GDSII workflow training. Covered Synthesis → Place & Route → Timing Closure → Sign-off — full tapeout flow.

🎯 Core Competency Map

🔬 VLSI & Semiconductor	🛠️ Embedded & IoT	🧠 Deep Learning & Edge AI	💻 Programming & Env
`RTL Design` `Synthesis` `Physical Design` `STA & Timing` `CMOS Circuits` `DRC / LVS` `Floorplanning` `Clock Tree Synthesis`	`ARM Cortex-M4` `STM32F4VE` `NXP Platforms` `Raspberry Pi` `Arduino Ecosystem` `Custom PCB` `Sensor Fusion` `IoT Protocols`	`CNN Architectures` `YOLO Detection` `ResNet Recognition` `Siamese MobileNet` `Model Quantization` `Edge Deployment` `TensorFlow / PyTorch` `Computer Vision`	`C / C++` `Python` `Bash / Shell` `Verilog HDL` `SPICE Netlists` `Linux CLI` `Git` `SQL`

🐧 Environments & Scripting

_Linux

_CentOS

_Ubuntu

_C

_C++

_Python

_Bash

🧩 Problem Solving

_{Programming Problems}

_{DSA Problems}

📊 GitHub Analytics

🌿 Beyond the Bench

🏋️ Weight Training

Structured progressive overload routines.
Discipline at the rack fuels discipline at the bench.

🌱 Indoor Botanist

Monsteras · Pothos · Chunky substrates · Moss poles.
Growing silicon by day, growing green by night.

🔧 Also builds — Frontend & Web (Tailwind · GSAP · Three.js)

_Tailwind

_Three.js

_GSAP

_HTML

_CSS

🐍 Contribution Graph

🤝 Let's Connect

⚡ "The fault, dear engineer, is not in our stars, but in our netlists."

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