agent: add gk7605v100

CLAUDE.md

@@ -57,7 +57,7 @@ node --test web/protocol.test.js web/profile-parity.test.js
 # Cross-compile flash agent (ARM32; needs arm-none-eabi-gcc + newlib)
 make -C agent                   # default: SOC=hi3516ev300
 make -C agent SOC=hi3516cv300   # specific SoC
-make -C agent all-socs          # only 4 representative SoCs, not all 10
+make -C agent all-socs          # only 4 representative SoCs, not all 11
 ```
 
 Apart from the single-test and cross-compile lines, those are exactly what the
@@ -82,7 +82,7 @@ five CI jobs in `.github/workflows/ci.yml` run (`test`, `fuzz`, `lint`,
    `BootProtocol`, registered via the `@register` decorator and exposed as entry
    points in pyproject.toml:
    - `HiSiliconStandard` — matches **any chip that has a profile JSON**, i.e. all
-     112; classic init_bootmode handshake
+     113; classic init_bootmode handshake
    - `HiSiliconV500` — `gk7205v500/510/530`, `xm7205v500/510/530`; different handshake
    - `HiSiliconCV6xx` — `hi3516cv608/610/613`, `hi3516dv500`, `hi3519dv500`; multi-stage
 
@@ -126,13 +126,13 @@ the handshake, reverting to 115200 after ~30 s idle. 13 commands: `INFO 0x01`,
 optional features through a capability bitmask (`client.py`).
 
 Backends: `spi_flash.c` (fmc100), `spi_flash_hisfc350.c` (V1-era parts),
-`emmc_himci.c`. Ten SoCs are supported; each has its own `ifeq` stanza in
+`emmc_himci.c`. Eleven SoCs are supported; each has its own `ifeq` stanza in
 `agent/Makefile` carrying `LOAD_ADDR` (and `SPI_DRIVER` where it differs).
 `link.ld` itself is generic — it just places `. = LOAD_ADDR`.
 
 ### Other key modules
 
-- **Profiles** (`src/defib/profiles/`) — 112 JSON SoC definitions in `data/`,
+- **Profiles** (`src/defib/profiles/`) — 113 JSON SoC definitions in `data/`,
   validated with Pydantic (`schema.py`). `defib list-chips` combines those
   profiles with hardcoded V500/CV6xx chips and exact registered vendor-U-Boot
   migration selectors.

agent/Makefile

@@ -59,6 +59,16 @@ else ifeq ($(SOC),gk7205v300)
   WDT_BASE       = 0x12030000
   CRG_BASE       = 0x12010000
   SYSCTRL_REBOOT = 0x12020004
+else ifeq ($(SOC),gk7605v100)
+  UART_BASE      = 0x12040000
+  UART_CLOCK     = 24000000
+  LOAD_ADDR      = 0x41000000
+  FLASH_MEM      = 0x14000000
+  FMC_BASE       = 0x10000000
+  RAM_BASE       = 0x40000000
+  WDT_BASE       = 0x12030000
+  CRG_BASE       = 0x12010000
+  SYSCTRL_REBOOT = 0x12020004
 else ifeq ($(SOC),hi3516cv300)
   # V3 generation: ARM926EJ-S (ARMv5TEJ), not Cortex-A7.
   # UART is PL011 (same as ev300 family) at a different base.
@@ -178,7 +188,7 @@ else ifeq ($(SOC),hi3520dv200)
   SYSCTRL_REBOOT = 0x20050004
   SPI_DRIVER     = hisfc350
 else
-  $(error Unknown SOC: $(SOC). Supported: hi3516ev300 hi3516ev200 gk7205v200 gk7205v300 hi3516cv300 hi3516cv500 hi3518ev200 hi3516cv610 hi3519v101 hi3520dv200)
+  $(error Unknown SOC: $(SOC). Supported: hi3516ev300 hi3516ev200 gk7205v200 gk7205v300 gk7605v100 hi3516cv300 hi3516cv500 hi3518ev200 hi3516cv610 hi3519v101 hi3520dv200)
 endif
 
 # Per-SoC CPU. V3 chips (cv300) are ARM926EJ-S (ARMv5TEJ);

agent/README.md

@@ -74,6 +74,7 @@ Requires `arm-none-eabi-gcc` (Arch: `pacman -S arm-none-eabi-gcc arm-none-eabi-n
 | hi3516ev200 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 |
 | gk7205v200 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 |
 | gk7205v300 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 |
+| gk7605v100 | 0x12040000 | 0x14000000 | 0x40000000 | 0x41000000 |
 | hi3516cv300 | 0x12100000 | 0x14000000 | 0x80000000 | 0x81000000 |
 | hi3516cv500 | 0x12100000 | 0x14000000 | 0x80000000 | 0x81000000 |
 | hi3518ev200 | 0x12100000 | 0x14000000 | 0x80000000 | 0x81000000 |

src/defib/agent/client.py

@@ -152,6 +152,7 @@ def bad_block(self) -> list[SectorResult]:
     "gk7205v200": "gk7205v200",
     "gk7205v300": "gk7205v200",
     "gk7202v300": "gk7205v200",
+    "gk7605v100": "gk7205v200",
     "hi3516cv300": "hi3516cv300",
     "hi3516cv500": "hi3516cv500",
     "hi3516av300": "hi3516cv500",  # cv500-family, same memory map