Digital Logic Minimizer & Gate-Level Realizer

Overview

This project is a C++ implementation of:

• Quine–McCluskey Algorithm
• Petrick’s Method
• NAND/NOR Gate-Level Realization

The program minimizes Boolean expressions and converts them into optimized logic gate implementations.

It supports both:

• SOP (Sum of Products)
• POS (Product of Sums)

forms along with don't-care conditions.

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Features

• Quine–McCluskey Boolean minimization
• Petrick’s Method implementation
• Essential Prime Implicant selection
• Support for don't-care conditions
• SOP and POS simplification
• Truth table generation
• NAND-only realization
• NOR-only realization
• Gate count estimation
• Interactive CLI interface

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Algorithms Used

1. Quine–McCluskey Algorithm

Used for systematic Boolean expression minimization by:

• Grouping minterms
• Combining terms differing by one bit
• Finding prime implicants
• Selecting essential prime implicants

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2. Petrick’s Method

Used when multiple prime implicant combinations exist.

It helps find:

• Minimal cover solutions
• Optimized Boolean expressions

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3. Gate-Level Realization

The minimized expressions are converted into:

• NAND-only circuits
• NOR-only circuits

which are universal gate implementations used in digital hardware design.

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Technologies Used

• C++
• STL
• Boolean Algebra
• Digital Logic Design
• Quine–McCluskey Method
• Petrick’s Method

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Project Structure

.
├── logic_minimizer.cpp
├── README.md

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Compilation

Linux / macOS

g++ logic_minimizer.cpp -O2 -o logic
./logic

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Menu Options

1. Quine-McCluskey (Heuristic Method)
2. Quine-McCluskey (Petrick's Method)
3. Gate-level realization (NAND/NOR only)

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Input Supported

SOP Example

F(A,B,C,D) = Σ(1,3,7,11,15)

POS Example

F(A,B,C,D) = Π(0,2,5,8)

Don't-Care Terms

d(4,6,9)

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Output Features

The program generates:

• Minimized Boolean expression
• Prime implicants
• Truth table verification
• NAND/NOR gate implementation
• Total gate count

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Example Features

Boolean Minimization

Input:

Minterms: 1 3 7 15

Output:

A'B + CD

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Gate-Level Realization

Example:

NAND(A,B) -> T1
NAND(T1,C) -> F

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Advantages

• Fully algorithmic minimization
• Handles large Boolean expressions
• Supports don't-care optimization
• Hardware-level realization support
• Educational and practical implementation