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Fix CI #26

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Merged
rohanku merged 2 commits into from
Sep 1, 2026
Merged

Fix CI #26

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57dd57e
Fix CI
rohanku Sep 1, 2026
eebdd21
fix stale ucie.h
rohanku Sep 1, 2026
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8 changes: 8 additions & 0 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,14 @@ jobs:
build:
name: Compile, elaborate, and check generated collateral
runs-on: ubuntu-latest
# Chisel's FIRRTL converter recurses over expression trees, and Iris's are deep
# enough to overflow the runner's default 1 MB stack inside Converter.convertPrim,
# aborting the suite before a single test runs. The heap goes up with it: a runner
# defaults to a quarter of its 16 GB, which is tight for elaborating a chip top.
# JAVA_TOOL_OPTIONS is what reaches the JVM mill forks to run the tests in, which is
# where elaboration actually happens.
env:
JAVA_TOOL_OPTIONS: -Xmx6g -Xss8m
steps:
- uses: actions/checkout@v4

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102 changes: 46 additions & 56 deletions software/ucie.h
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Expand Up @@ -52,16 +52,13 @@
#define UCIE_CLK_PHASE_SEL 0x3d8ULL
#define UCIE_CLK_FREQ_SEL 0x3e0ULL
#define UCIE_TXCTL 0x3e8ULL
#define UCIE_TXCTL_DLL_RESET_OFS 0x0ULL
#define UCIE_TXCTL_DRIVER_OFS 0x8ULL
#define UCIE_TXCTL_SKEW_OFS 0x10ULL
#define UCIE_TXCTL_SHUFFLER_OFS 0x18ULL
#define UCIE_TXCTL_TILE_OFS 0x0ULL
#define UCIE_TXCTL_SHUFFLER_OFS 0x8ULL
#define UCIE_TXCTL_SHUFFLER_WIDTH 0x8ULL
#define UCIE_TXCTL_SAMPLE_NEGEDGE_OFS 0x118ULL
#define UCIE_TXCTL_DELAY_OFS 0x120ULL
#define UCIE_TXCTL_DLL_CODE_OFS 0x128ULL
#define UCIE_TXCTL_WIDTH 0x130ULL
#define UCIE_RXCTL 0x1cd8ULL
#define UCIE_TXCTL_SAMPLE_NEGEDGE_OFS 0x108ULL
#define UCIE_TXCTL_DELAY_OFS 0x110ULL
#define UCIE_TXCTL_WIDTH 0x118ULL
#define UCIE_RXCTL 0x1ae0ULL
#define UCIE_RXCTL_ZEN_OFS 0x0ULL
#define UCIE_RXCTL_ZCTL_OFS 0x8ULL
#define UCIE_RXCTL_VREF_SEL_OFS 0x10ULL
Expand All @@ -74,49 +71,46 @@
#define UCIE_RXCTL_SAMPLE_NEGEDGE_OFS 0x138ULL
#define UCIE_RXCTL_RX_DELAY_OFS 0x140ULL
#define UCIE_RXCTL_WIDTH 0x148ULL
#define UCIE_DEBUG_TX_TEST_MODE 0x37c0ULL
#define UCIE_DEBUG_TX_DATA_MODE 0x37c8ULL
#define UCIE_DEBUG_TX_LFSR_SEED 0x37d0ULL
#define UCIE_DEBUG_TX_FSM_RST 0x37d8ULL
#define UCIE_DEBUG_TX_EXECUTE 0x37e0ULL
#define UCIE_DEBUG_TX_MANUAL_REPEAT_PERIOD 0x37e8ULL
#define UCIE_DEBUG_TX_PACKETS_TO_SEND 0x37f0ULL
#define UCIE_DEBUG_DATA 0x37f8ULL
#define UCIE_DEBUG_TX_TEST_MODE 0x35c8ULL
#define UCIE_DEBUG_TX_DATA_MODE 0x35d0ULL
#define UCIE_DEBUG_TX_LFSR_SEED 0x35d8ULL
#define UCIE_DEBUG_TX_FSM_RST 0x35e0ULL
#define UCIE_DEBUG_TX_EXECUTE 0x35e8ULL
#define UCIE_DEBUG_TX_MANUAL_REPEAT_PERIOD 0x35f0ULL
#define UCIE_DEBUG_TX_PACKETS_TO_SEND 0x35f8ULL
#define UCIE_DEBUG_DATA 0x3600ULL
#define UCIE_DEBUG_DATA_WIDTH 0x8ULL
#define UCIE_DEBUG_DRIVERCTL 0x3878ULL
#define UCIE_DEBUG_DRIVERCTL 0x3680ULL
#define UCIE_DEBUG_DRIVERCTL_WIDTH 0x8ULL
#define UCIE_DEBUG_TXCTL_DLL_RESET 0x3898ULL
#define UCIE_DEBUG_TXCTL_DRIVER 0x38a0ULL
#define UCIE_DEBUG_TXCTL_SKEW 0x38a8ULL
#define UCIE_DEBUG_TXCTL_SHUFFLER 0x38b0ULL
#define UCIE_DEBUG_TXCTL_TILE 0x36a0ULL
#define UCIE_DEBUG_TXCTL_SHUFFLER 0x36a8ULL
#define UCIE_DEBUG_TXCTL_SHUFFLER_WIDTH 0x8ULL
#define UCIE_DEBUG_TXCTL_DLL_CODE 0x39b0ULL
#define UCIE_DEBUG_TX_TEST_STATE 0x39b8ULL
#define UCIE_DEBUG_TX_PACKETS_SENT 0x39c0ULL
#define UCIE_DEBUG_CLK_MUX_SEL 0x39c8ULL
#define UCIE_DEBUG_RX_LANE 0x39d0ULL
#define UCIE_DEBUG_RX_BIT 0x39d8ULL
#define UCIE_TX_VALID 0x39e0ULL
#define UCIE_RX_LFSR_VALID 0x39e8ULL
#define UCIE_CONTROLLER_SEL 0x39f0ULL
#define UCIE_MAINBAND_MODE 0x39f8ULL
#define UCIE_SIDEBAND_MODE 0x3a00ULL
#define UCIE_CREDIT_FLOW_ENABLE 0x3a08ULL
#define UCIE_TX_VALID_LANE_SEL 0x3a10ULL
#define UCIE_RX_VALID_LANE_SEL 0x3a18ULL
#define UCIE_LAST_SEEN_TL_REQ 0x3a20ULL
#define UCIE_SB_TX_PACKET 0x3a28ULL
#define UCIE_SB_TX_SEND 0x3a30ULL
#define UCIE_SB_TX_BUSY 0x3a38ULL
#define UCIE_SB_RX_PACKET 0x3a40ULL
#define UCIE_SB_RX_VALID 0x3a48ULL
#define UCIE_SB_RX_POP 0x3a50ULL
#define UCIE_SB_RX_OVERFLOW 0x3a58ULL
#define UCIE_SB_RX_RST 0x3a60ULL
#define UCIE_SB_TL_RX_OVERFLOW 0x3a68ULL
#define UCIE_UCIE_LINK_RESET 0x3a70ULL
#define UCIE_UCIE_PWR_GOOD 0x3a78ULL
#define UCIE_UCIE_RETRY_TRAINING_AMT 0x3a80ULL
#define UCIE_DEBUG_TX_TEST_STATE 0x37a8ULL
#define UCIE_DEBUG_TX_PACKETS_SENT 0x37b0ULL
#define UCIE_DEBUG_CLK_MUX_SEL 0x37b8ULL
#define UCIE_DEBUG_RX_LANE 0x37c0ULL
#define UCIE_DEBUG_RX_BIT 0x37c8ULL
#define UCIE_TX_VALID 0x37d0ULL
#define UCIE_RX_LFSR_VALID 0x37d8ULL
#define UCIE_CONTROLLER_SEL 0x37e0ULL
#define UCIE_MAINBAND_MODE 0x37e8ULL
#define UCIE_SIDEBAND_MODE 0x37f0ULL
#define UCIE_CREDIT_FLOW_ENABLE 0x37f8ULL
#define UCIE_TX_VALID_LANE_SEL 0x3800ULL
#define UCIE_RX_VALID_LANE_SEL 0x3808ULL
#define UCIE_LAST_SEEN_TL_REQ 0x3810ULL
#define UCIE_SB_TX_PACKET 0x3818ULL
#define UCIE_SB_TX_SEND 0x3820ULL
#define UCIE_SB_TX_BUSY 0x3828ULL
#define UCIE_SB_RX_PACKET 0x3830ULL
#define UCIE_SB_RX_VALID 0x3838ULL
#define UCIE_SB_RX_POP 0x3840ULL
#define UCIE_SB_RX_OVERFLOW 0x3848ULL
#define UCIE_SB_RX_RST 0x3850ULL
#define UCIE_SB_TL_RX_OVERFLOW 0x3858ULL
#define UCIE_UCIE_LINK_RESET 0x3860ULL
#define UCIE_UCIE_PWR_GOOD 0x3868ULL
#define UCIE_UCIE_RETRY_TRAINING_AMT 0x3870ULL

// === Constants ===
#define UCIE_TX_TEST_STATE_IDLE 0x0ULL
Expand All @@ -137,7 +131,7 @@
#define UCIE_DEFAULT_VALID 0xf0f0f0fULL
#define UCIE_DEFAULT_TRACK 0x55555555ULL
#define UCIE_ENABLE_DRIVER_CTL 0x3ffeULL
#define UCIE_DEFAULT_SKEW_CTL 0xbf80c296ULL
#define UCIE_ENABLE_TX_CTL 0x1fff000000000ULL

// === Helper functions ===
static inline void reset_fsms(uintptr_t base) {
Expand All @@ -159,23 +153,19 @@ static inline void write_rxctl(uintptr_t base, uint64_t lane, uint64_t ofs, uint

static inline void setup_ucie(uintptr_t base) {
for (int lane = 0; lane < 21; lane++) {
write_txctl(base, lane, UCIE_TXCTL_DLL_RESET_OFS, 0x0ULL);
write_txctl(base, lane, UCIE_TXCTL_DRIVER_OFS, UCIE_ENABLE_DRIVER_CTL);
write_txctl(base, lane, UCIE_TXCTL_SKEW_OFS, UCIE_DEFAULT_SKEW_CTL);
write_txctl(base, lane, UCIE_TXCTL_TILE_OFS, UCIE_ENABLE_TX_CTL);
write_rxctl(base, lane, UCIE_RXCTL_ZEN_OFS, 0x1ULL);
write_rxctl(base, lane, UCIE_RXCTL_ZCTL_OFS, 0x0ULL);
}
reg_write64(base + UCIE_TX_CLK_P, UCIE_DEFAULT_CLK_P);
reg_write64(base + UCIE_TX_CLK_N, UCIE_DEFAULT_CLK_N);
reg_write64(base + UCIE_TX_VALID, UCIE_DEFAULT_VALID);
reg_write64(base + UCIE_RX_LFSR_VALID, UCIE_DEFAULT_VALID);
reg_write64(base + UCIE_DEBUG_TXCTL_DLL_RESET, 0x0ULL);
reg_write64(base + UCIE_DIV_RESETB, 0x1ULL);
for (int i = 0; i < 4; i++) {
reg_write64(base + UCIE_DEBUG_DRIVERCTL + 8 * i, UCIE_ENABLE_DRIVER_CTL);
}
reg_write64(base + UCIE_DEBUG_TXCTL_DRIVER, UCIE_ENABLE_DRIVER_CTL);
reg_write64(base + UCIE_DEBUG_TXCTL_SKEW, UCIE_DEFAULT_SKEW_CTL);
reg_write64(base + UCIE_DEBUG_TXCTL_TILE, UCIE_ENABLE_TX_CTL);
reset_fsms(base);
reg_write64(base + UCIE_CONTROLLER_SEL, UCIE_CONTROLLER_SEL_PHYTEST);
reg_write64(base + UCIE_MAINBAND_MODE, UCIE_BAND_MODE_MANUAL);
Expand Down
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