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Merged
rohanku merged 2 commits into from
Sep 1, 2026
Merged

Bump UCIe and fix CI #25

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83664ee
Bump UCIe
rohanku Sep 1, 2026
5d91ff3
fix CI errors
rohanku Sep 1, 2026
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44 changes: 44 additions & 0 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,50 @@ jobs:
key: ${{ runner.os }}-mill-${{ hashFiles('build.mill', 'module.mill') }}
restore-keys: ${{ runner.os }}-mill-

# Elaboration shells out to the device tree compiler, which rocket-chip runs to
# build the DTB the boot ROM embeds, and it is not on the runner image. Installing
# it through apt would cost an `apt-get update` first -- tens of MB of indexes to
# land 223 KB of dtc -- so fetch the package and its two dependencies from the
# archive pool instead. Pinned by version and checksum, which is also what makes
# the plain-HTTP fetch safe; apt verifies its downloads the same way. If the pool
# ever drops these versions the curl 404s and the apt path takes over.
- name: Install the device tree compiler
run: |
set -euo pipefail
pool=http://archive.ubuntu.com/ubuntu/pool/main
cd "$(mktemp -d)"
if curl -fsSLO "$pool/d/device-tree-compiler/device-tree-compiler_1.7.0-2build1_amd64.deb" \
&& curl -fsSLO "$pool/d/device-tree-compiler/libfdt1_1.7.0-2build1_amd64.deb" \
&& curl -fsSLO "$pool/liby/libyaml/libyaml-0-2_0.2.5-1build1_amd64.deb"; then
sha256sum --check <<'SUMS'
b2c1e8c86f18b6bda26408f92bfb9ec1a1e40bfdc41f1034600ccd68e82d2ed7 device-tree-compiler_1.7.0-2build1_amd64.deb
274d20dfab9d6b216b5de85446a93f6ce5b2cd82c847b8dfdc508577f76eb96a libfdt1_1.7.0-2build1_amd64.deb
f5271b120d936dcc7ddf17b9e718df41d55386a6075555d0c634925eaef0b2ac libyaml-0-2_0.2.5-1build1_amd64.deb
SUMS
sudo dpkg -i ./*.deb
else
echo "Archive pool no longer serves the pinned versions; falling back to apt."
sudo apt-get update
sudo apt-get install -y --no-install-recommends device-tree-compiler
fi
dtc --version

# Constellation builds its routing tables with Chisel's `decoder`, which uses
# espresso when it is on the PATH and otherwise falls back to Quine-McCluskey
# with nothing but a logged error. QMC is exponential on tables this size, so
# the fallback exhausts the runner's heap and aborts the suite.
- name: Install espresso
env:
ESPRESSO_SHA256: 7683c4315e1c9cec293c194eb6a1ed716d22a9952a96bd88bff62ecf57df6e2f
run: |
set -euo pipefail
mkdir -p "$HOME/.local/bin"
curl -fsSL -o "$HOME/.local/bin/espresso" \
https://github.com/chipsalliance/espresso/releases/download/v2.4/x86_64-linux-gnu-espresso
echo "$ESPRESSO_SHA256 $HOME/.local/bin/espresso" | sha256sum --check
chmod +x "$HOME/.local/bin/espresso"
echo "$HOME/.local/bin" >> "$GITHUB_PATH"

- name: Compile
run: ./mill test.compile

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2 changes: 1 addition & 1 deletion ucie
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Submodule ucie updated 39 files
+32 −6 rs/src/verilog/tx.rs
+15 −0 scala/resources/vsrc/pad_driver.v
+38 −0 scala/resources/vsrc/sb_driver.v
+0 −28 scala/resources/vsrc/ser21.v
+0 −88 scala/resources/vsrc/tx_driver.v
+63 −255 scala/resources/vsrc/tx_lane.v
+25 −30 scala/src/phy/Phy.scala
+9 −13 scala/src/phy/SidebandSerial.scala
+97 −0 scala/src/phy/macros/PadDriver.scala
+96 −0 scala/src/phy/macros/SbDriver.scala
+125 −662 scala/src/phy/macros/Tx.scala
+10 −13 scala/src/phytest/PhyTest.scala
+12 −40 scala/src/tilelink/Codegen.scala
+30 −53 scala/src/tilelink/TileLink.scala
+7 −2 scala/src/uciedigital/logphy/LogicalPhy.scala
+8 −2 scala/src/uciedigital/logphy/utils/Bundles.scala
+11 −4 scala/src/uciedigital/sideband/LogPhySidebandChannel.scala
+12 −5 scala/src/uciedigital/sideband/modules/SidebandLinkNode.scala
+15 −16 scala/src/uciedigital/sideband/modules/SidebandLinkSerdes.scala
+0 −17 scala/src/uciedigital/utils/Ser21.scala
+3 −0 scala/test/src/Utils.scala
+16 −2 scala/test/src/phy/SidebandSerialSpec.scala
+96 −0 scala/test/src/phy/macros/TxLaneCtlSpec.scala
+17 −2 scala/test/src/phytest/PhyTestDebugBumpsSpec.scala
+35 −7 scala/test/src/phytest/PhyTestDebugLaneSpec.scala
+17 −2 scala/test/src/phytest/PhyTestFramingSpec.scala
+36 −7 scala/test/src/phytest/PhyTestLoopbackSpec.scala
+16 −2 scala/test/src/phytest/SidebandTestSpec.scala
+0 −1 scala/test/src/tilelink/TileLinkSpec.scala
+17 −2 scala/test/src/uciedigital/loopback/LogPhyLoopbackHarness.scala
+17 −2 scala/test/src/uciedigital/loopback/UcieDigitalLoopbackHarness.scala
+15 −2 scala/test/src/uciedigital/loopback/UcieMmioBringupHarness.scala
+25 −1 scala/test/src/uciedigital/sideband/SidebandChannelRandomTest.scala
+2 −2 scala/test/src/uciedigital/sideband/SidebandLinkNodeTest.scala
+52 −33 scala/test/src/uciedigital/sideband/SidebandLinkSerdesTest.scala
+28 −7 verilog/constants.vams
+81 −67 verilog/phy.sv
+114 −538 verilog/tx.sv
+224 −40 verilog/tx.vams
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