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Merged
aswaterman merged 1 commit into from
Aug 19, 2026
Merged

Explicitly truncate wide-RHS assignments #93

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2 changes: 1 addition & 1 deletion hardfloat/src/main/scala/DivSqrtRecFN_small.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -357,7 +357,7 @@ class
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val bitMask = (1.U<<cycleNum)(sigWidth + 2, 0)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
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6 changes: 3 additions & 3 deletions hardfloat/src/main/scala/MulAddRecFN.scala
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Expand Up @@ -138,8 +138,8 @@ class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule

//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddA := rawA.sig(sigWidth - 1, 0)
io.mulAddB := rawB.sig(sigWidth - 1, 0)
io.mulAddC := alignedSigC(sigWidth * 2, 1)

io.toPostMul.isSigNaNAny :=
Expand All @@ -155,7 +155,7 @@ class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
Mux(CIsDominant, rawC.sExp, (sExpAlignedProd - sigWidth.S)(expWidth + 1, 0).asSInt)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
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