soft-error

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

Thesis work of Daniele Rizzieri - 2021

Soft Error Vulnerability Analysis Framework for Xilinx FPGAs

Fault Injector for LLVM based on LLFI project.

Timing-aware SET fault injection for gate-level netlists: propagates SET pulses with SDF information, then reports which flip-flops capture them as upset probabilities and multi-bit upset patterns.

Sustained fault injection for RISC-V over the DFT scan chain — flip bits in real FFs at any cycle while the processor runs