This project implements a 4-bit pseudo-random number generator (PRNG) on the Basys 3 FPGA board using Verilog. The PRNG is designed using a Linear Feedback Shift Register (LFSR) with a tapped XOR feedback mechanism.

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

Analysis of RISC-V Linux boot process using QEMU and OpenSBI with architectural state inspection for checkpointing research.