This repository features the design and FPGA implementation of a complete MCU-style digital system built around a pipelined MIPS processor core. Features a multi-stage pipeline for maximized instruction throughput, complete with integration wrapper modules and system-level components optimized for hardware deployment.
pipelined-processor-design rtl-hardware-implementation fpga-based-digital-system-design system-level-digital-design modular-hardware-integration
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Updated
May 21, 2026 - VHDL