A modular, open-source Power Management Unit (PMU) integrated into the PULP Croc SoC — an open-source RISC-V SoC based on the CVE2 (Ibex) core. Implements clock gating and power gating via UPF (IEEE 1801), using a fully open-source RTL-to-GDSII flow.
systemverilog risc-v power-management open-source-hardware upf power-gating pulp-platform clock-gating croc-soc
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Updated
May 7, 2026 - SystemVerilog