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chili-chips-ba / openPCIE

Star 109

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to Gbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port in 4 ways: |1| openRTL |2| openBFM with unique SIM and WAVE capabilities, way better than vendor's |3| openSW stack |4| one-of-a-kind open backplane.

fpga serdes driver pcb rtl backplane systemverilog rp pcie bfm
  • Updated Oct 17, 2026
  • SystemVerilog

chili-chips-ba / openCologne-PCIE

Star 100

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...

acceleration asic ai fpga simulation pipe pcb vip rtl verilog endpoint m2 pcie
  • Updated Oct 17, 2026
  • Verilog

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