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full-custom-layout

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oluwaferanmi-arowoshola / vedic-multiplier-vlsi-design

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Full-custom 8-bit pipelined Vedic multiplier in 90nm CMOS with hierarchical schematic/layout design, DRC/LVS-clean verification, post-layout simulation, and 50 MHz pipelined operation.

spice computer-architecture vlsi semiconductor cmos digital-design lvs drc circuit-design timing-analysis synopsys-custom-compiler layout-design physical-verification full-custom-layout vedic-multiplier pipelined-architecture
  • Updated May 16, 2026

Rakesh-2306 / Performance-Balanced-Noise-Canceling-Low-Noise-Amplifier

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Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

calibre cadence-virtuoso mixed-signal rf-analysis linearity noise-cancellation stability-analysis low-noise-amplifier lna noise-analysis cadence-spectre s-parameter design-rule-check design-for-manufacturability scl180nm full-custom-layout parasitic-extraction layout-vs-schematic custom-spiral-inductor
  • Updated Apr 14, 2026

Rakesh-2306 / Design-and-analysis-of-Low-power-hybrid-full-adder-for-array-multiplier-in-90nm-technology

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Designed and implemented a low-power hybrid full adder and 4-bit/8-bit array multipliers in GPDK 90nm CMOS using Cadence Virtuoso, including schematic design, full-custom layout, DRC/LVS verification, PEX, and post-layout performance analysis.

cadence-virtuoso low-power full-adder low-power-comsumption assura array-multiplier post-layout-simulation design-rule-check low-power-design transmission-gate-logic full-custom-layout layout-vs-schematic gpdk90nm
  • Updated Oct 21, 2025

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