🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

CPU Benchmarks Set

LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

Benchmarks set written in C#, Java, PHP, JS, Python, Lua, Go

Dhrystone/Whetstone benchmark for esp-idf

Embedded system single board system performance benchmarks

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.

"DHRYSTONE" Benchmark Program by Reinhold P. Weicker. Forked from SiFive repository.

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

Dhrystone Benchmark measurement calculation for complexity of integer computation performed on ESP 32