Multiprocessor Simulator with two levels of Cache hierarchy.
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Oct 11, 2015 - C++
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cache-hierarchy
Here are 6 public repositories matching this topic...
Experiments to simulate multiple cache hierarchies, L1/L2 set-associativities, block sizes using DineroIV, and measure impact on Cycles Per Instruction (CPI) and Average Memory Access Time (AMAT).
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Nov 26, 2019 - Python
Configurable L1+L2 cache hierarchy simulator with LRU replacement and write-back/write-allocate policy, written in C++
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Apr 15, 2026 - C++
An open-source hardware simulator and live telemetry engine for generative AI. Track total system resource utilization in real-time across storage, memory paths, and compute blocks to eliminate black-box execution failures.
memory-management gpu-computing computer-architecture cache-hierarchy hardware-software-co-design generative-ai llm-inference bottleneck-analysis system-telemetry
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May 24, 2026 - Rust
A high-performance MIPS processor simulator written in Rust, featuring both functional and advanced timing simulations. Explore pipelined execution, Tomasulo's algorithm for out-of-order execution, multi-level cache hierarchies, and sophisticated branch prediction. Ideal for computer architecture education, research, and CPU design.
rust debugging simulator mips processor architecture pipelining hazard-detection timing-simulator mips-processor tomasulo cpu-simulator functional-simulator cache-hierarchy
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Aug 22, 2025 - Rust
A collection of computer architecture simulators for pipeline scheduling, cache hierarchy behavior, and branch prediction
python perceptron computer-architecture cache-simulator branch-prediction branch-predictor pipeline-simulator cache-hierarchy gshare out-of-order-execution
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May 21, 2026 - Python
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