PowerRiser – NVMe 2230 and 2242 Expansion board for Lenovo Tiny 5 Series
Implements multi-protocol market data parsing supporting NASDAQ (UDP/MoldUDP64), ASX (TCP/SoupBinTCP), and B3 Brazilian Exchange (UDP/SBE) market data feeds. Integrates with Project 33's 10GBASE-R PHY for 10GbE reception and outputs parsed messages via Aurora to FPGA2 (order book engine).
This project integrates the ALINX 10GbE UDP vendor design with a UART debug interface for monitoring network traffic and system status. It serves as the foundation for ITCH market data reception on the AX7325B (Kintex-7 XC7K325T) FPGA.
A complete custom implementation of the 10GBASE-R Physical Layer (PHY) in VHDL. This implementation provides full control over the 10 Gigabit Ethernet physical layer without relying on encrypted vendor IP.
This project implements a 10 Gigabit Ethernet (10GbE) interface using the Kintex-7 GTX transceivers on the ALINX AX7325B board. It uses the open-source [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) library for the MAC/PHY layers.
Order Book 10GbE - FPGA Order Book with UDP TX and Latency Measurement
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