[agicy]

Summary

Switch build targets to soft-float variants:

• AArch64: aarch64-unknown-none -> aarch64-unknown-none-softfloat
• RISC-V: riscv64gc-unknown-none-elf -> riscv64imac-unknown-none-elf
• LoongArch: loongarch64-unknown-none -> loongarch64-unknown-none-softfloat

No source code changes are included.

Motivation

hvisor does not need hardware floating-point or SIMD support in the
hypervisor itself. Using the soft-float variants makes that explicit at the
Rust target level instead of relying on per-board flags.

Verification

Installed the required targets:

rustup target add aarch64-unknown-none-softfloat
rustup target add riscv64imac-unknown-none-elf
rustup target add loongarch64-unknown-none-softfloat

Build and link verification:

make ARCH=aarch64 BOARD=qemu-gicv3 defconfig
make ARCH=aarch64 BOARD=qemu-gicv3 elf
make ARCH=riscv64 BOARD=qemu-aia defconfig
make ARCH=riscv64 BOARD=qemu-aia elf
make ARCH=loongarch64 BOARD=ls3a5000 defconfig
make ARCH=loongarch64 BOARD=ls3a5000 elf

Results:

aarch64/qemu-gicv3    PASS
riscv64/qemu-aia      PASS
loongarch64/ls3a5000  PASS

Risks and Limitations

LoongArch changes to rust-lld.

[peikachu]

Switching to aarch64-unknown-none-softfloat loses the Cortex-A53 erratum 843419 workaround.

On the pinned toolchain (nightly-2024-05-05), the aarch64-unknown-none target spec passes --fix-cortex-a53-843419 to the linker, but aarch64-unknown-none-softfloat does not. This PR therefore silently drops the workaround on A53 boards.

This affects zcu102, imx8mp and ok6254-c (all have Cortex-A53 in their device trees). Their current release builds contain no affected instruction sequence (the linker applies 0 patches even with the workaround enabled), so nothing is broken today, but later code or layout changes may introduce one. Please add this to those boards' cargo/config.template.toml:

"-Clink-arg=--fix-cortex-a53-843419",

[li041]

LGTM!