GitHub - sujoyyyy/VLSI: Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.

Repository navigation

VLSI

Public

Notifications
Fork (0)
Star (2)

About

Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.

cmos magic simulation spice-simulation verilog vlsi-circuits xilinx

Activity

2 stars

1 watching

Name		Name	Last commit message	Last commit date
Magic_tcl files		Magic_tcl files
Verilog_codes		Verilog_codes
.gitattributes		.gitattributes

About

Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.

cmos magic simulation spice-simulation verilog vlsi-circuits xilinx

Activity

2 stars

1 watching

0 forks

Report repository

Navigation Menu

Repository navigation

About

About

Releases

Packages

Contributors

Languages

Latest commit

History

Folders and files

About

Topics

Stars

Watchers

Forks

Releases

Packages

Contributors

Languages