Add support for the Cadence SD6 SDHCI controller#581
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paulmenzel
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May 26, 2026
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Please send the patch upstream for review (the tool b4 helps, or normal git commands git format-patch … and git send-email …).
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| From d1910de6f9c5de27eecf89dc12a165a600aac833 Mon Sep 17 00:00:00 2001 | |||
| From: rnair <rnair@marvell.com> | |||
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| struct nix_lf_alloc_rsp with hw_rx_tstamp_en to match the mbox | ||
| structure with applications. | ||
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| Signed-off-by: rnair <rnair@marvell.com> |
…r for octeon platform This includes enabling the Cadence SD6 controller, HS400/HS400ES modes, ACPI integration, PHY delay tuning, and multiple fixes for timing, tuning, and controller corner cases. Also updated the OTX2 mailbox interface version and related structures. Why I did it ------------ Octeon platforms require specific controller handling and tuning for reliable high-speed eMMC operation. Existing driver support lacked MMC Controller-specific configurations, resulting in instability and incorrect operation in HS400-class modes. Additionally, mailbox structure updates were needed to align kernel and application interfaces How I verified it ----------------- - Booted Octeon platform with updated driver - Verified eMMC enumeration and initialization - Tested HS400 / HS400ES mode transitions - Validated tuning execution and value population - Verified mailbox compatibility with updated structure Details if related ------------------ - Added Cadence SD6 SDHCI controller support - Enabled HS400 and HS400ES modes - Configured PHY delays and default tuning values when DT values are missing or invalid - Implemented delay element handling and Cadence-specific tuning logic, including multi-block read helpers - Improved handling of DDR, clocking, enhanced strobe, command delay, block gap, and interrupt corner cases - Added ACPI support for Octeon Cadence SDHCI instance - Updated OTX2_MBOX_VERSION to 0x000b - Extended struct nix_lf_alloc_rsp with hw_rx_tstamp_en Patch upstreaming plan ---------------------- - These patches are not to be upstreamed. - There are parallel threads in Progress to give sd6hc support, which needs to be evaluated first: https://lkml.org/lkml/2026/5/11/2580 Signed-off-by: Renjithkumar Raveendran Nair <rnair@marvell.com>
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What I did
Added support for Cadence Sdhci eMMC controller for octeon platform.
This includes enabling the Cadence SD6 controller, HS400/HS400ES modes,
ACPI integration, PHY delay tuning, and multiple fixes for timing,
tuning, and controller corner cases.
Also updated the OTX2 mailbox interface version and related structures.
Why I did it
Octeon platforms require specific controller handling and tuning for reliable
high-speed eMMC operation. Existing driver support lacked MMC
Controller-specific configurations, resulting in instability and incorrect
operation in HS400-class modes. Additionally, mailbox structure updates
were needed to align kernel and application interfaces
How I verified it
Details if related
Patch upstreaming plan