A Digital Voting Machine developed as a Digital Logic Design (CEN2007) project using Proteus and Verilog. The system automates vote counting using sequential and combinational logic while enforcing a secure voting limit of 40 votes.
This project demonstrates the implementation of a secure 6-bit digital voting machine. Votes are stored digitally and updated in real time. The system automatically stops accepting votes once the predefined limit of 40 votes is reached.
- Automated digital vote counting
- 6-bit memory architecture
- Maximum vote limit of 40
- Real-time LED output
- Proteus circuit simulation
- Verilog timing verification
- Digital Logic Design
- Verilog HDL
- Proteus Design Suite
- Sequential Logic
- Combinational Logic
- Input Stage – Vote buttons and reset
- Processing Stage – Vote increment logic
- Memory Stage – 6-bit vote storage
- Security Stage – 40-vote limit detection
- Output Stage – LED vote display
The system continuously monitors the vote count. Once the total reaches 40 votes, additional votes are blocked automatically to prevent over-voting.
Digital-Voting-Machine-DLD/
│
├── source
├── report
├── assets
│ └── screenshots
├── README.md
└── LICENSE
- Download or clone this repository.
- Open the Proteus project located in the source folder.
- Review the simulation and project report.
- Analyze the Verilog timing diagram.
- Seven-segment display support
- BCD counter implementation
- FPGA implementation
- Duplicate vote prevention
- Audible notification system
- Saman Saeed
- Noor Fatima
- Shumaila Batool
Supervisor: LE Rabia Asad
The complete project report is available in the report folder.
This project is licensed under the MIT License.
Saman Saeed
BS Computer Engineering
National University of Technology (NUTECH), Islamabad