explain how SIMD relates to SIMT, SPMD, scalable hardware, and tensors

[enthropy7]

Part of #29. My third PR in the series.

Adds the conceptual "how does SIMD relate to other models and hardware" material, placed right after Quick Background so it reads as the landscape before the vocabulary.

Fills these checklist gaps:

• Differences between CPU SIMD and GPU SIMT
• Differences between SIMD vectors and SPMD threads
• Differences between "wide vectors" and "vector architectures" (Cray, RISC-V V, Arm SVE)

added two new sections:

• SIMD, SIMT, and SPMD - warp/wavefront and divergence; why a vector's lanes aren't independent threads (lockstep, masking instead of branches); ISPC as SPMD-on-CPU-SIMD.
• Fixed-Width vs. Scalable Vectors - packed SSE/AVX/NEON vs. length-agnostic Cray/RVV/SVE (RVV vsetvl, SVE vector length-agnostic loops), with concrete widths in the wild (A64FX 512-bit, Graviton3 256-bit, most Armv9 mobile 128-bit).
  Notes that portable-simd's fixed-size types lower to scalable instructions where that's better, but it has no variable-size types yet - expanding on the point @programmerjake raised in explain SIMD terminology and commonly-confused terms #535.

NB: the issue already had "SIMD vectors vs SPMD threads" checked, but the guide had no text on it, which was corrected in this PR.

[workingjubilee]

My thinking has changed somewhat over time and I don't really think we need a bunch of documentation on tensors and all that anymore.

[enthropy7]

My thinking has changed somewhat over time and I don't really think we need a bunch of documentation on tensors and all that anymore.

so, we should get rid of tensors and related stuff here?

[workingjubilee]

Sorry, to clarify, by "all that" I mean this entire PR's contents. My apologies.