drivers: add Realtek Bee UDC and SDHC drivers - #312
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The DWC2 USB driver was accessing hardware registers through a raw dev->config->base pointer, which breaks on MMU-enabled platforms where physical addresses need to be mapped to virtual ones before use. Use Zephyr's standard MMIO abstraction API by introducing DEVICE_MMIO_NAMED_RAM/ROM(core) in the driver's data and config structs, mapping the region at initialization time with DEVICE_MMIO_NAMED_MAP, and routing all register accesses through a dwc2_get_base() helper that calls DEVICE_MMIO_NAMED_GET. These changes allows the driver to be useful on MMU-based platforms like Broadcom BCM2711 SoC. Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com> (cherry picked from commit 0d158a6) upstream-status: available
Use one file per vendor quirk. No modification to any content, only the same code being moved to separate files. Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no> (cherry picked from commit 57f0805) upstream-status: available
Fix below warnings on 64bit platforms:
drivers/usb/udc/udc_dwc2.c: In function 'dwc2_tx_fifo_write':
rivers/usb/udc/udc_dwc2.c:454:29: warning: cast from pointer to
integer of different size [-Wpointer-to-int-cast]
454 | sys_write32((uint32_t)buf->data,
| ^
drivers/usb/udc/udc_dwc2.c: In function 'dwc2_prep_rx':
drivers/usb/udc/udc_dwc2.c:651:29: warning: cast from pointer to
integer of different size [-Wpointer-to-int-cast]
651 | sys_write32((uint32_t)data,
| ^
drivers/usb/udc/udc_dwc2.c: In function 'dwc2_read_fifo_setup':
drivers/usb/udc/udc_dwc2.c:2324:25: warning: format '%d' expects argument
of type 'int', but argument 2 has type 'size_t' {aka 'long unsigned int'}
2324 | LOG_ERR("%d bytes SETUP", size);
| ^~~~~~~~~~~~~~~~ ~~~~
| |
| size_t {aka long unsigned int}
include/zephyr/logging/log_core.h:336:50: note: in definition of macro
'Z_LOG2'
336 | z_log_printf_arg_checker(__VA_ARGS__);
| ^~~~~~~~~~~
include/zephyr/logging/log.h:62:22: note: in expansion of macro 'Z_LOG'
62 | #define LOG_ERR(...) Z_LOG(LOG_LEVEL_ERR, __VA_ARGS__)
| ^~~~~
drivers/usb/udc/udc_dwc2.c:2324:17: note: in expansion of macro 'LOG_ERR'
2324 | LOG_ERR("%d bytes SETUP", size);
| ^~~~~~~
drivers/usb/udc/udc_dwc2.c:2324:27: note: format string is defined here
2324 | LOG_ERR("%d bytes SETUP", size);
| ~^
| |
| int
| %ld
drivers/usb/udc/udc_dwc2.c: In function 'dwc2_handle_oepint':
drivers/usb/udc/udc_dwc2.c:2615:51: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
2615 | sys_cache_data_invd_range((void *)(addr - 8), 8);
| ^
drivers/usb/udc/udc_dwc2.c:2616:45: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
2616 | memcpy(priv->setup, (void *)(addr - 8), sizeof(priv->setup));
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
(cherry picked from commit 5f1892d)
upstream-status: available
Add USB device driver support for Synaptics SR100 devices. Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com> (cherry picked from commit e682185) upstream-status: available
Add Infineon vendor quirks to the UDC DW2 implementation. This ties to the infineon,usbhs binding. Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com> (cherry picked from commit 059fca3) upstream-status: available
Call disable quirk if controller initialization fails. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no> (cherry picked from commit 0e0d804) upstream-status: available
After DWC2 core is disabled the registers should no longer be accessed to prevent CPU hangs. While the concurrent access is guarded by mutex, there was no mechanism to ensure that driver thread won't access any register after udc_disable() was called. Solve the issue by executing disable in driver thread context. Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no> (cherry picked from commit d40884d) upstream-status: available
Introduce a shared Espressif USB-OTG binding scheme and rename the existing full-speed quirk to the speed specific espressif,esp32-usb-otg-fs compatible. The internal PHY D+/D- pad numbers now come from the phy-dp-pin and phy-dm-pin device tree properties, so migrate the esp32s3 node accordingly. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com> (cherry picked from commit cb7f6f9) upstream-status: available
The Realtek Bee rtl87x2g USB core is a DesignWare OTG (DWC2) instance driven by the generic udc_dwc2 driver. Add a vendor quirk (udc_dwc2_realtek_bee.h), selected from the "realtek,bee-udc" compatible: the .init hook runs the PHY power sequence from the prebuilt Realtek USB HAL and the .caps hook advertises High-Speed, control MPS0 and remote-wakeup. Also add the binding, the udc@40100000 node in the rtl87x2g dtsi, and the board-level enable on rtl87x2g_evb_a. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add an SDHC driver for the Realtek Bee series SoCs (RTL87X2G), on top of the vendor HAL controller (internal IDMAC). Features: - Full sdhc driver API (reset, request, set_io, get_card_present, card_busy, get_host_props, SDIO enable/disable_interrupt) - IDMAC single- and multi-block read and write with auto-stop - SD erase (CMD32/CMD33/CMD38) - 1-bit and 4-bit bus widths, legacy/high-speed timing, up to 50 MHz - Hardware automatic clock gating - Data-transfer error recovery (datapath reset + CMD12) - Write-path SUSPEND-state recovery via poll-demand - 50 MHz read Descriptor-Unavailable re-poll - Power sequencing with optional power GPIO and host reset on power-on - SDIO card interrupt via GPIO pin - Optional interrupt tracing (CONFIG_SDHC_BEE_ISR_TRACE) Includes the RTL87X2G devicetree node, the realtek,bee-sdhc binding, Kconfig, and the SoC linker sections for the HAL blob's .app.* regions. Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Enable the USB mass storage sample on rtl87x2g_evb_a/rtl8762gku by describing the SDHC0 pins, bus width and the sdmmc-disk block device. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add a disk_access test suite for the Realtek Bee SDHC controller,
targeting rtl87x2g_evb_a/rtl8762gku with a card in the SD slot.
The suite exercises the driver through the disk_access API:
- Card detection: when both the SDMMC and MMC disk drivers are built,
probe the MMC volume ("SD2") before the SDMMC volume ("SD") and keep
whichever one initializes for the inserted card. The SDMMC init path
falls through to MMC init on failure, so probing it first would
mis-bind an eMMC to the SD-only erase command set (CMD32/33); probing
MMC first avoids that.
- Single- and multi-block reads and writes at several sector counts,
with an overflow canary to catch buffer overruns.
- Physical erase of a small range and of the whole card.
- Power-cycle stress via DISK_IOCTL_CTRL_DEINIT/CTRL_INIT.
- FAT format and fs-level trim.
On RTL87X2G the scratch buffers are cache-line aligned so the SD stack
issues real multi-block CMD18/CMD25 transfers instead of bouncing
single blocks through the per-card buffer.
CONFIG_SD_CMD_TIMEOUT is raised to 30 s: a whole-card erase (CMD38)
holds the card busy on DAT0 far longer than the 200 ms default. With
the default the host reports a response timeout and the still-erasing
card then poisons every subsequent command.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
The Realtek Bee rtl87x2j USB core is another DesignWare OTG (DWC2) instance driven by the generic udc_dwc2 driver. Extend the existing vendor quirk (udc_dwc2_realtek_bee.h) to cover CONFIG_SOC_SERIES_RTL87X2J: the .init hook runs hal_usb_phy_power_on() from the prebuilt Realtek USB HAL and the .disable hook runs hal_usb_phy_power_down(), while the .caps hook keeps advertising High-Speed, control MPS0 and remote-wakeup. Also add the udc@40100000 node in the rtl87x2j dtsi and the board-level enable on rtl87x2j_evb rtl8762jth. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add key4(GPIOA_13, P2_1) and key5(GPIOA_17, P2_5) for rtl87x2j_evb_rtl8762jth board. Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add HAL_REALTEK_BEE_LPC and HAL_REALTEK_BEE_SPI3W for LPC/SPI3W. Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
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Add two Realtek Bee rtl87x2g drivers, plus the board overlays to validate them
on
rtl87x2g_evb_a/rtl8762gku.UDC (DesignWare DWC2 vendor quirk)
The Bee USB core is a DesignWare OTG (DWC2) instance driven by the generic
udc_dwc2driver. The Realtek-specific bring-up is audc_dwc2vendor quirk(
udc_dwc2_realtek_bee.h):.initruns the PHY power sequence from the prebuilt Realtek USB HAL(
hal_usb_phy_power_on/hal_rtk_usb_init); the power routines already teardown the boot-ROM MPU region guarding the USB speed registers, so no direct
register access is needed here.
.disable/.shutdowncallusb_rtk_disable_power_seq()..capsadvertises High-Speed, remote-wakeup and control MPS0 = 64.Adds
dts/bindings/usb/realtek,bee-udc.yaml(includessnps,dwc2.yaml),the
udc@40100000node in the SoC dtsi, and a board-level enable onrtl87x2g_evb_a.SDHC
The Bee SDHC controller driver (
drivers/sdhc/sdhc_bee.c) sits on the prebuiltRealtek HAL. Adds:
dts/bindings/sdhc/realtek,bee-sdhc.yamland thesdhc0SoC node.copied and get the right MPU permissions at boot
(
.app.ram.text→.ramfunc,.app.ram.data→.data); left as orphansections they fault.
Board bring-up / validation overlays
Both overlays describe SDHC0 (P9_4 CLK, P9_3 CMD, P10_0/P9_7/P9_6/P9_5 D0–D3,
4-bit bus, 20 MHz) and a
zephyr,sdmmc-diskblock device namedSDonrtl87x2g_evb_a/rtl8762gku:tests/drivers/disk/disk_access— exercises the SDHC driver directly.samples/subsys/usb/mass— exercises both drivers together: USB MSC (UDC)backed by the SD card (SDHC).