drivers: crypto: bee: add PSA hardware accelerator driver

bee/drivers/crypto/CMakeLists.txt

@@ -3,3 +3,6 @@
 
 zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
 zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
+
+add_subdirectory_ifdef(CONFIG_CRYPTO_BEE_PSA_ACCELERATOR psa)

bee/drivers/crypto/inc/rtl8752h/hw_aes.h

@@ -77,6 +77,74 @@ typedef enum
     */
 extern bool hw_aes_decrypt_16byte(uint8_t *input, uint8_t *output);
 
+/**
+    * @brief  128 bit AES encryption on specified plain data and keys
+    *
+    * @param[in]  p_in              specified plain data to be encrypted
+    * @param[out] p_out             output buffer to store encrypted data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+extern bool hw_aes_encrypt128(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                              uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+/**
+    * @brief  128 bit AES decryption on specified data and keys
+    *
+    * @param[in]  p_in              specified encrypted data to be decrypted
+    * @param[out] p_out             output buffer to store plain data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+extern bool hw_aes_decrypt128(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                              uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+/**
+    * @brief  256 bit AES encryption on specified plain data and keys
+    *
+    * @param[in]  p_in              specified plain data to be encrypted
+    * @param[out] p_out             output buffer to store encrypted data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+extern bool hw_aes_encrypt256(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                              uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+/**
+    * @brief  256 bit AES decryption on specified data and keys
+    *
+    * @param[in]  p_in              specified encrypted data to be decrypted
+    * @param[out] p_out             output buffer to store plain data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+extern bool hw_aes_decrypt256(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                              uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
 /**
     * @brief  128 bit AES encryption via DMA on specified plain data and keys
     *

bee/drivers/crypto/inc/rtl87x2g/crypto_engine_nsc.h

@@ -83,6 +83,17 @@ typedef struct
     uint8_t buffer[64];         /*!< The data block being processed. */
     int is224;                  /*!< unused, just align mbedtls structure */
 } HW_SHA256_CTX;
+
+/** @brief AES mode definition for HW AES. */
+typedef enum
+{
+    AES_MODE_NONE,
+    AES_MODE_CBC,
+    AES_MODE_ECB,
+    AES_MODE_CFB,
+    AES_MODE_OFB,
+    AES_MODE_CTR
+} T_HW_AES_MODE;
 /** End of CRYPTO_ENGINE_Exported_Types
   * @}
   */
@@ -142,6 +153,83 @@ bool hw_sha256_cpu_update(HW_SHA256_CTX *ctx, uint8_t *input, uint32_t byte_len)
     */
 bool hw_sha256_finish(HW_SHA256_CTX *ctx, uint32_t *result);
 
+/**
+    * @brief  128 bit AES encryption on specified plain data and keys
+    *
+    * @param[in]  p_in              specified plain data to be encrypted
+    * @param[out] p_out             output buffer to store encrypted data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_aes_encrypt128(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                       uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+/**
+    * @brief  128 bit AES decryption on specified data and keys
+    *
+    * @param[in]  p_in              specified encrypted data to be decrypted
+    * @param[out] p_out             output buffer to store plain data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_aes_decrypt128(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                       uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+/**
+    * @brief  256 bit AES encryption on specified plain data and keys
+    *
+    * @param[in]  p_in              specified plain data to be encrypted
+    * @param[out] p_out             output buffer to store encrypted data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_aes_encrypt256(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                       uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+/**
+    * @brief  256 bit AES decryption on specified data and keys
+    *
+    * @param[in]  p_in              specified encrypted data to be decrypted
+    * @param[out] p_out             output buffer to store plain data
+    * @param[in]  data_word_len     input buffer length in 32-bit words
+    * @param[in]  p_key             key buffer
+    * @param[in]  p_iv              initialization vector
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_aes_decrypt256(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                       uint32_t *p_key, uint32_t *p_iv, T_HW_AES_MODE mode);
+
+void hw_pke_clock(bool enable);
+void hw_pke_init(bool byte_swap_en, bool word_swap_en, uint32_t word_swap_base);
+void hw_ecc_init(uint32_t key_bits, PKE_MODE mode, bool go_to_end_loop,
+                 bool RR_mod_n_ready);
+void hw_ecc_set_sub_operand(uint32_t operand_addr, uint32_t *operands,
+                            uint32_t byte_len);
+bool hw_ecc_set_all_operands(ECC_GROUP *grp, uint32_t *e, uint32_t e_byte_size);
+ERR_CODE hw_ecc_compute(void *result, uint32_t output_addr, uint16_t func_id);
+
 /** End of CRYPTO_ENGINE_Exported_Functions
   * @}
   */
@@ -150,4 +238,4 @@ bool hw_sha256_finish(HW_SHA256_CTX *ctx, uint32_t *result);
   * @}
   */
 
-#endif
+#endif

bee/drivers/crypto/inc/rtl87x2j/aes_dma_types.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+#ifndef __AES_DMA_TYPES_H
+#define __AES_DMA_TYPES_H
+
+#include <stdint.h>
+
+typedef void (*AES_DMA_CB)(void *);
+typedef void (*AES_DMA_ISR)(void);
+
+typedef struct AES_DMA_CFG
+{
+    uint8_t dma_ch_num;
+    AES_DMA_ISR dma_isr;
+    AES_DMA_CB cb;
+    void *cb_param;
+} AES_DMA_CFG;
+
+#endif /* __AES_DMA_TYPES_H */

bee/drivers/crypto/inc/rtl87x2j/aes_interface.h

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+#ifndef __AES_INTERFACE_H
+#define __AES_INTERFACE_H
+// *INDENT-OFF*
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Includes ------------------------------------------------------------------*/
+#include <stdbool.h>
+#include <stdint.h>
+#include "aes_dma_types.h"
+
+#define AES_SUPPORT_DMA_MODE    1
+#define AES_SUPPORT_CMAC        1
+
+typedef enum
+{
+    AES_NONE,
+    AES_CBC = 0x1,
+    AES_ECB = 0x2,
+    AES_CFB = 0x3,
+    AES_OFB = 0x4,
+    AES_CTR_IV_64BITS_MSB = 0x5,
+    AES_CTR_IV_96BITS_MSB = 0x15,
+    AES_CTR_IV_64BITS_LSB = 0x25,
+    AES_CTR_IV_96BITS_LSB = 0x35,
+    AES_CIPHER_MAC = 0x6,
+} AES_WORK_MODE;
+
+typedef enum
+{
+    AES_KEY_IRK = 0,
+    AES_KEY2 = 1,
+    AES_KEY3 = 2,
+    AES_KEY4 = 3,
+    AES_KEY5 = 4,
+    AES_HIDDEN_KEY,
+    AES_KEY_MAX,
+} AES_KEY_SEL;
+
+typedef enum
+{
+    AES_KEY_BITS_128 = 128,
+    AES_KEY_BITS_256 = 256,
+} AES_KEY_BITS_SEL;
+
+typedef struct
+{
+    uint32_t *key;
+    AES_KEY_BITS_SEL key_bits;
+    AES_KEY_SEL key_sel;
+} AES_KEY_CFG;
+
+typedef enum
+{
+    AES_CPU_MODE = 0,
+    AES_DMA_MODE = 1,
+} AES_ACCESS_MODE;
+
+typedef struct
+{
+    uint32_t *input;
+    uint32_t *iv;
+    uint32_t byte_len;
+    AES_WORK_MODE aes_mode;
+    AES_ACCESS_MODE access_mode;
+#if AES_SUPPORT_DMA_MODE == 1
+    AES_DMA_CFG *dma_rx_cfg;
+    AES_DMA_CFG *dma_tx_cfg;
+#endif
+} AES_CFG;
+
+void aes_init(AES_WORK_MODE aes_mode, const uint32_t *iv, AES_KEY_CFG *key_cfg);
+bool aes_cpu_operate(const uint32_t *in, uint32_t *out, uint32_t word_len, bool isEncrypt);
+bool aes_encrypt(AES_CFG *aes_config, AES_KEY_CFG *key_cfg, uint32_t *ciphertext);
+bool aes_decrypt(AES_CFG *aes_config, AES_KEY_CFG *key_cfg, uint32_t *plaintext);
+
+#if AES_SUPPORT_DMA_MODE == 1
+void aes_dma_channel_init(AES_DMA_CFG *rx_cfg, AES_DMA_CFG *tx_cfg);
+bool aes_dma_operate(const uint32_t *in, uint32_t *out, uint32_t word_len, bool isEncrypt);
+bool aes_dma_done(void);
+#endif
+
+#if AES_SUPPORT_CMAC == 1
+typedef struct
+{
+    uint8_t *input;
+    uint32_t byte_len;
+    AES_ACCESS_MODE access_mode;
+    AES_DMA_CFG *dma_rx_cfg;
+} AES_CMAC_CFG;
+
+bool aes_cmac(AES_CMAC_CFG *cmac_config, AES_KEY_CFG *key_cfg, uint32_t *cmac);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__AES_INTERFACE_H*/

bee/drivers/crypto/inc/rtl87x2j/sha2_interface.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+#ifndef __SHA2_INTERFACE_H
+#define __SHA2_INTERFACE_H
+// *INDENT-OFF*
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Includes ------------------------------------------------------------------*/
+#include <stdbool.h>
+#include <stdint.h>
+
+#define SHA2_SUPPORT_DMA_MODE       1
+#define SHA2_DMA_CH_NUM             2U
+
+typedef enum
+{
+    SHA2_DMA_MODE = 0,
+    SHA2_CPU_MODE = 1,
+} SHA2_ACCESS_MODE;
+
+typedef enum
+{
+    SHA2_224,
+    SHA2_256,
+    SHA2_ALGO_MAX,
+} SHA2_ALGO;
+
+typedef struct
+{
+    uint32_t total[2];
+    uint32_t state[8];
+    uint8_t buffer[64];
+    SHA2_ALGO algo;
+} SHA2_CTX;
+
+typedef struct
+{
+    uint8_t *input;
+    uint32_t byte_len;
+    SHA2_ALGO algo;
+    SHA2_ACCESS_MODE access_mode;
+    uint8_t dma_ch_num;
+} SHA2_CFG;
+
+void sha2_init(void);
+void sha2_start(SHA2_CTX *ctx, SHA2_ALGO algo);
+bool sha2_cpu_update(SHA2_CTX *ctx, const uint8_t *input, uint32_t byte_len);
+bool sha2_cpu_finish(SHA2_CTX *ctx, uint32_t *output);
+uint32_t sha2_get_digest_len(SHA2_ALGO algo);
+void sha2_iv_init(SHA2_ALGO algo, uint32_t *iv);
+void sha2_get_digest(SHA2_ALGO algo, uint32_t *output);
+
+#if SHA2_SUPPORT_DMA_MODE == 1
+void sha2_dma_channel_init(uint8_t dma_rx_ch_num);
+bool sha2_dma_update(SHA2_CTX *ctx, const uint8_t *input, uint32_t byte_len);
+bool sha2_dma_finish(SHA2_CTX *ctx, uint32_t *output);
+#endif
+
+bool sha2(SHA2_CFG *sha2_config, uint32_t *result);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__SHA2_INTERFACE_H*/