A single-file, browser-based simulator for GAL16V8, GAL20V8, and GAL22V10 PLD fuse maps (JED files). Load a real JED, watch it decode into per-pin logic equations, then flip switches and pulse the clock on a virtual breadboard to see exactly how your design behaves — before you burn it into a chip.
Also works with the Microchip/Atmel ATF16V8C / ATF20V8 / ATF22V10C parts, since they're JEDEC-fuse-map-identical to the Lattice originals.
Created to help validate PAL/GAL logic before you programme the chip.
- Three devices, one tool — auto-detects GAL16V8 / GAL20V8 / GAL22V10 from
the JED's
*QFfuse count (or theDevice:header text, including ATF part numbers), with a manual override dropdown if auto-detect ever gets it wrong. - Interactive virtual breadboard — every pin renders as a switch (input), an LED (output), or a plain label (GND/VCC/NC), laid out on a DIP package outline matching the real pin count (20-pin or 24-pin).
- Real clocking — the CLK pin's switch fires an actual clock pulse on its low→high transition. A separate "Pulse CLOCK" button is also there for quickly firing repeated pulses.
- Decoded logic panel — for every output pin: registered vs combinatorial,
active-high vs active-low, how its output-enable is determined (always on,
always off, a shared
/OEpin, or its own product term), and its full driving equation (sum-of-products for combinatorial outputs, the D-input for registered ones). GAL22V10's async-reset/sync-preset (AR/SP) terms are shown too. - Optional pin-name file — pair a JED with a
.pinfile to show real signal names instead of bare pin numbers (format below). - NC-aware rendering — a pin named
NCin the pin map never gets a switch or LED, regardless of what the device architecture would otherwise allow there, so unused pins don't clutter the board. - Three worked examples built in — a BCD-to-7-segment decoder (GAL22V10), a 4-bit synchronous counter with carry-out (GAL16V8), and a 74138-style 3-to-8 line decoder (GAL20V8) — each exercising a different architecture mode.
- No build step — it's one HTML file. Open it in a browser and it works.
Just open the HTML file in any modern browser. There's no server, no build step, and no dependencies.
- Load a JED via the file picker, or click Load example to try one of the three built-in demos for whichever device is selected.
- Optionally load a
.pinfile to replace the genericP14-style labels with real signal names. - Flip input switches to set the combinatorial inputs you want to test.
- Pulse the clock — either flip the CLK switch low→high, or click Pulse CLOCK ↑ — to advance any registered outputs. Space bar does the same thing while focus isn't on a button/input/select.
- Read the Decoded Logic panel on the right for the actual equation driving each pin.
- Use Reset switches / All inputs LOW / All inputs HIGH to quickly reset the board, and the Device dropdown if you need to override auto-detection for a file that isn't a standard GAL16V8/20V8/22V10 fuse map.
A .pin file is plain text, one pin per line:
Pin # | Name | Pin Type
-----------------------------
1 | PHI2 | Clock/Input
2 | A15 | Input
12 | GND | GND
14 | LORAM | Output
24 | VCC | VCC
Only the pin number and name columns are used; the "Pin Type" column and the
header/separator rows are ignored. Name a pin NC to suppress its switch/LED
entirely.
-
GAL16V8/GAL20V8 fuse-map layout (the SYN/AC0/AC1/XOR/PTD architecture control bits, and the mode-dependent AND-array column assignments) was verified against the GALasm reference implementation, cross-checked against the Lattice/Atmel datasheets.
-
AR (async reset) is only evaluated when the clock is pulsed, not continuously as switches change. This matches SP's real synchronous behavior.
-
GAL22V10's registered-macrocell feedback is from
/Qregardless of output polarity (a documented quirk of that specific device) GAL16V8/20V8 feedback is the plain post-polarity pin value.
Open source - see MIT LICENSE for details.
Created by Derek Robson. Another Asinine Project from asinine-labs.org.