Rework RX/TX buffering and queues

Bender.yml

@@ -55,7 +55,7 @@ sources:
     - src/regs/hyperbus_cfg_regblock.sv
     - src/hyperbus_cfg_regs.sv
     - src/backend/hyperbus_phy.sv
-    - src/hyperbus_axi.sv
+    - src/hyperbus_axi_frontend.sv
     - src/hyperbus_atomic_handler.sv
     - src/hyperbus_midend.sv
     - src/hyperbus_cfg_frontend.sv
@@ -77,4 +77,6 @@ sources:
         - test/dut_if.sv
         - test/hyperbus_tb_pkg.sv
         - test/axi_hyper_tb.sv
+        - test/hyperbus_atomic_handler_tb.sv
         - test/hyperbus_cfg_regs_tb.sv
+        - test/axi_pre_aw_drain_tb.sv

include/hyperbus/typedef.svh

@@ -5,6 +5,10 @@
 `ifndef HYPERBUS_TYPEDEF_SVH_
 `define HYPERBUS_TYPEDEF_SVH_
 
+////////////////////////////////
+// Protocol-neutral host link //
+////////////////////////////////
+
 `define HYPERBUS_TYPEDEF_HOST_CMD_T(__name, __addr_t) \
   typedef struct packed {                               \
     logic                             write;             \
@@ -68,7 +72,11 @@
   `HYPERBUS_TYPEDEF_HOST_RSP_T(__name``_rsp_t, __name``_r_t,              \
                                __name``_wrsp_t)
 
-`define HYPERBUS_TYPEDEF_LINK_ALL_CT(__name, __num_phys, __num_chips) \
+////////////////////////////
+// Midend-to-backend link //
+////////////////////////////
+
+`define HYPERBUS_TYPEDEF_LINK_ALL_CT(__name, __num_phys)              \
   typedef struct packed {                                             \
     logic [(16*__num_phys)-1:0] data;                                 \
     logic                       last;                                 \
@@ -84,7 +92,7 @@
   } __name``_wrsp_t;                                                  \
   typedef struct packed {                                             \
     hyperbus_pkg::hyper_tf_t trans;                                   \
-    logic [__num_chips-1:0]  cs;                                      \
+    logic [hyperbus_pkg::HyperNumChips-1:0] cs;                        \
   } __name``_cmd_t;                                                   \
   typedef struct packed {                                             \
     __name``_cmd_t  cmd;                                              \

scripts/start.tcl

@@ -41,6 +41,8 @@ run_test axi_hyper_tb_isochronous          sim_run_isochronous.wlf
 run_test axi_hyper_tb_synchronous          sim_run_synchronous.wlf
 run_test axi_hyper_tb_asynchronous         sim_run_asynchronous.wlf
 run_test axi_hyper_tb_synchronous_one_phy  sim_run_synchronous_one_phy.wlf
+run_test hyperbus_atomic_handler_tb        sim_run_atomic_handler.wlf
 run_test hyperbus_cfg_regs_tb              sim_run_cfg_regs.wlf
+run_test axi_pre_aw_drain_tb                sim_run_pre_aw_drain.wlf
 
 quit -code $regression_failed -f

src/backend/hyperbus_backend.sv

@@ -6,7 +6,6 @@
 `include "common_cells/registers.svh"
 
 module hyperbus_backend #(
-    parameter int unsigned  NumChips         = -1,
     parameter int unsigned  NumPhys          = 2,
     parameter int unsigned  StartupCycles    = 60000,
     parameter int unsigned  SyncStages       = 2,
@@ -31,7 +30,7 @@ module hyperbus_backend #(
     input  hyper_req_t                 req_i,
     output hyper_rsp_t                 rsp_o,
 
-    output logic [NumPhys-1:0][NumChips-1:0] hyper_cs_no,
+    output logic [NumPhys-1:0][hyperbus_pkg::HyperNumChips-1:0] hyper_cs_no,
     output logic [NumPhys-1:0]               hyper_ck_o,
     output logic [NumPhys-1:0]               hyper_ck_no,
     output logic [NumPhys-1:0]               hyper_rwds_o,
@@ -43,12 +42,15 @@ module hyperbus_backend #(
     output logic [NumPhys-1:0]               hyper_reset_no
 );
 
+    /////////////////////////////
+    // Configuration and clock //
+    /////////////////////////////
+
     hyperbus_pkg::phy_cfg_t cfg_q;
-    logic                     cfg_apply_accepted;
-    logic                     phy_busy_any;
-    logic                     clk_tx;
+    logic                   cfg_apply_accepted;
+    logic                   phy_busy_any;
+    logic                   clk_tx;
 
-    `ASSERT_INIT(NumChipsValid, NumChips >= 1 && NumChips <= 8)
     `ASSERT_INIT(NumPhysValid, NumPhys == 1 || NumPhys == 2)
     `ASSERT_INIT(SyncStagesValid, SyncStages >= 2)
 
@@ -69,6 +71,10 @@ module hyperbus_backend #(
         .out_o   ( clk_tx               )
     );
 
+    /////////////////////
+    // Physical lanes //
+    /////////////////////
+
     if (NumPhys == 2) begin : gen_dual_phy
         hyperbus_pkg::phy_rx_t [NumPhys-1:0] phy_rx;
         hyperbus_pkg::phy_rx_t [NumPhys-1:0] buffered_rx;
@@ -169,7 +175,6 @@ module hyperbus_backend #(
             );
 
             hyperbus_phy #(
-                .NumChips       ( NumChips       ),
                 .StartupCycles  ( StartupCycles  ),
                 .NumPhys        ( NumPhys        ),
                 .SyncStages     ( SyncStages     )
@@ -211,7 +216,6 @@ module hyperbus_backend #(
         end
     end else begin : gen_single_phy
         hyperbus_phy #(
-            .NumChips       ( NumChips       ),
             .StartupCycles  ( StartupCycles  ),
             .NumPhys        ( NumPhys        ),
             .SyncStages     ( SyncStages     )

src/backend/hyperbus_clock_diff_out.sv

@@ -9,28 +9,27 @@
 (* no_ungroup *)
 (* no_boundary_optimization *)
 (* keep_hierarchy = "yes" *)
-module hyperbus_clock_diff_out
-(
+module hyperbus_clock_diff_out (
     input  logic in_i,
-    input  logic en_i, //high enable
+    input  logic en_i,
     output logic out_o,
     output logic out_no
 );
 
-   `ifdef FPGA_EMUL
+`ifdef FPGA_EMUL
 
-       logic en_sync;
+    logic en_sync;
 
-       always_latch
-       begin
-         if (in_i == 1'b0)
-           en_sync <= en_i;
-       end
+    always_latch begin
+        if (in_i == 1'b0) begin
+            en_sync <= en_i;
+        end
+    end
 
-       assign out_o = in_i & en_sync;
-       assign out_no = ~out_o;
+    assign out_o  = in_i & en_sync;
+    assign out_no = ~out_o;
 
-   `else
+`else
 
     tc_clk_gating i_hyper_ck_gating (
         .clk_i     ( in_i  ),
@@ -44,6 +43,6 @@ module hyperbus_clock_diff_out
         .clk_o ( out_no )
     );
 
-   `endif // !`ifdef FPGA_EMUL
+`endif
 
 endmodule

src/backend/hyperbus_ddr_out.sv

@@ -7,7 +7,7 @@
 
 module hyperbus_ddr_out #(
     parameter logic Init = 1'b0
-)(
+) (
     input  logic clk_i,
     input  logic rst_ni,
     input  logic d0_i,
@@ -18,21 +18,21 @@ module hyperbus_ddr_out #(
     logic q1;
 
 `ifdef FPGA_EMUL
-       always_comb
-      begin
-        if(clk_i == 1'b0)
-           q_o = q1;
-        else
-           q_o = q0;
-      end
+    always_comb begin
+        if (clk_i == 1'b0) begin
+            q_o = q1;
+        end else begin
+            q_o = q0;
+        end
+    end
 `else
     tc_clk_mux2 i_ddrmux (
         .clk_o     ( q_o   ),
         .clk0_i    ( q1    ),
         .clk1_i    ( q0    ),
         .clk_sel_i ( clk_i )
     );
-`endif // !`ifdef FPGA_EMUL
+`endif
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if (~rst_ni) begin

src/backend/hyperbus_delay.sv

@@ -20,7 +20,7 @@ module hyperbus_delay (
     // Additional delay can be added for debug purposes,
     // the upper 3 bits are reserved for this optional additional delay
     configurable_delay #(
-      .NUM_STEPS(32)
+        .NUM_STEPS ( 32 )
     ) i_delay (
         .clk_i      ( in_i         ),
         .delay_i    ( delay_i[4:0] ),