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Hierarchical organisation of the register address map #39

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1,092 changes: 914 additions & 178 deletions docs/regs/hyperbus_cfg_regs.md
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619 changes: 414 additions & 205 deletions include/hyperbus_cfg_regs.h
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28 changes: 15 additions & 13 deletions scripts/gen_regs.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -12,35 +12,37 @@ export UV_CACHE_DIR
export UV_TOOL_DIR

RDL="${ROOT}/src/regs/hyperbus_cfg_regs.rdl"
PEAKRDL_ARGS=(
--from "peakrdl-cli==1.5.0"
--with "peakrdl-regblock==1.3.1"
--with "peakrdl-cheader==1.1.0"
--with "peakrdl-markdown==1.0.3"
)

mkdir -p "${ROOT}/include" "${ROOT}/docs/regs"
rm -rf "${ROOT}/docs/regs/hyperbus_cfg_regs"

uvx --from peakrdl-cli \
--with peakrdl-regblock \
--with peakrdl-cheader \
--with peakrdl-markdown \
uvx "${PEAKRDL_ARGS[@]}" \
peakrdl regblock \
--cpuif apb4-flat \
--default-reset arst_n \
--module-name hyperbus_cfg_regblock \
--package-name hyperbus_cfg_regblock_pkg \
--addr-width 7 \
--addr-width 12 \
-o "${ROOT}/src/regs" \
"${RDL}"

uvx --from peakrdl-cli \
--with peakrdl-regblock \
--with peakrdl-cheader \
--with peakrdl-markdown \
uvx "${PEAKRDL_ARGS[@]}" \
peakrdl c-header \
-o "${ROOT}/include/hyperbus_cfg_regs.h" \
"${RDL}"

uvx --from peakrdl-cli \
--with peakrdl-regblock \
--with peakrdl-cheader \
--with peakrdl-markdown \
uvx "${PEAKRDL_ARGS[@]}" \
peakrdl markdown \
-o "${ROOT}/docs/regs/hyperbus_cfg_regs.md" \
"${RDL}"

# Keep generated RTL compatible with the repository whitespace checks.
sed -i 's/[[:space:]]\+$//' \
"${ROOT}/src/regs/hyperbus_cfg_regblock.sv" \
"${ROOT}/src/regs/hyperbus_cfg_regblock_pkg.sv"
10 changes: 9 additions & 1 deletion src/hyperbus.sv
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Expand Up @@ -22,6 +22,7 @@ module hyperbus #(
parameter type axi_r_chan_t = logic,
parameter type axi_aw_chan_t = logic,
parameter int unsigned RegDataWidth = -1,
parameter int unsigned RegAddrWidth = 32,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
parameter type axi_rule_t = logic,
Expand Down Expand Up @@ -118,6 +119,8 @@ module hyperbus #(
.NumChips ( NumChips ),
.NumPhys ( NumPhys ),
.RegDataWidth ( RegDataWidth ),
.RegAddrWidth ( RegAddrWidth ),
.CapabilityFeatures ( '0 ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.rule_t ( axi_rule_t )
Expand All @@ -129,7 +132,12 @@ module hyperbus #(
.frontend_cfg_o ( frontend_cfg ),
.phy_cfg_o ( phy_cfg ),
.chip_rules_o ( chip_rules ),
.trans_active_i ( trans_active )
.trans_active_i ( trans_active ),
.cfg_busy_i ( trans_active ),
.decode_error_i ( 1'b0 ),
.cfg_dirty_i ( 1'b0 ),
.flush_req_o ( ),
.apply_req_o ( )
);

// AXI slave interfacing PHY
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255 changes: 165 additions & 90 deletions src/hyperbus_cfg_regs.sv
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1 change: 1 addition & 0 deletions src/hyperbus_synth_wrap.sv
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Expand Up @@ -146,6 +146,7 @@ module hyperbus_lint_wrap #(
.axi_r_chan_t ( r_chan_t ),
.axi_aw_chan_t ( aw_chan_t ),
.RegDataWidth ( RegDataWidth ),
.RegAddrWidth ( RegAddrWidth ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.axi_rule_t ( axi_rule_t )
Expand Down
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