Refactor HyperBus into asynchronous, isochronous, and synchronous variants

.gitignore

@@ -5,4 +5,7 @@ work/
 transcript
 modelsim.ini
 vsim.wlf
+sim_run*.wlf
+sim_*.log
 models/s27ks0641
+wlft*

Bender.yml

@@ -11,6 +11,9 @@ package:
     - "Paul Scheffler <paulsc@iis.ee.ethz.ch>"
     - "Luca Valente <luca.valente@unibo.it>"   # current maintainer
 
+export_include_dirs:
+  - include
+
 dependencies:
   common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.21.0        }
   axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1        }
@@ -39,31 +42,39 @@ sources:
 
     - target: any(test,all(not(hyperbus_exclude_dline),not(all(xilinx,hyperbus_dline))))
       files:
-        - src/hyperbus_delay.sv
+        - src/backend/hyperbus_delay.sv
 
     - src/regs/hyperbus_cfg_regblock_pkg.sv
     - src/hyperbus_pkg.sv
-    - src/hyperbus_clk_gen.sv
-    - src/hyperbus_clock_diff_out.sv
-    - src/hyperbus_w2phy.sv
-    - src/hyperbus_phy2r.sv
-    - src/hyperbus_ddr_out.sv
-    - src/hyperbus_trx.sv
+    - src/backend/hyperbus_tx_clk_delay.sv
+    - src/backend/hyperbus_clock_diff_out.sv
+    - src/hyperbus_write_adapter.sv
+    - src/hyperbus_read_adapter.sv
+    - src/backend/hyperbus_ddr_out.sv
+    - src/backend/hyperbus_trx.sv
     - src/regs/hyperbus_cfg_regblock.sv
     - src/hyperbus_cfg_regs.sv
-    - src/hyperbus_phy.sv
-    - src/hyperbus_phy_if.sv
+    - src/backend/hyperbus_phy.sv
     - src/hyperbus_axi.sv
+    - src/hyperbus_atomic_handler.sv
+    - src/hyperbus_midend.sv
+    - src/hyperbus_cfg_frontend.sv
+    - src/hyperbus_async_bridge.sv
+    - src/hyperbus_iso_bridge.sv
+    - src/backend/hyperbus_backend.sv
+    - src/hyperbus_synchronous.sv
+    - src/hyperbus_asynchronous.sv
+    - src/hyperbus_isochronous.sv
 
     - target: hyper_test
       files:
         # Device models. TODO: extend
         - models/s27ks0641/s27ks0641.v
         # Testbench
+        - test/hyperbus_test_dut.sv
         - test/fixture_hyperbus.sv
         - test/hyperbus_tb.sv
         - test/dut_if.sv
         - test/hyperbus_tb_pkg.sv
         - test/axi_hyper_tb.sv
         - test/hyperbus_cfg_regs_tb.sv
-    - src/hyperbus.sv

include/hyperbus/typedef.svh

@@ -0,0 +1,106 @@
+// Copyright 2026 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+`ifndef HYPERBUS_TYPEDEF_SVH_
+`define HYPERBUS_TYPEDEF_SVH_
+
+`define HYPERBUS_TYPEDEF_HOST_CMD_T(__name, __addr_t) \
+  typedef struct packed {                               \
+    logic                             write;             \
+    __addr_t                          addr;              \
+    hyperbus_pkg::hyper_blen_t        beats;             \
+    hyperbus_pkg::hyper_host_size_t   size;              \
+    hyperbus_pkg::hyper_host_burst_e  burst;             \
+    hyperbus_pkg::hyper_atomic_op_e   atomic_op;         \
+    logic                             atomic_return;     \
+    logic                             ordered;           \
+  } __name;
+
+`define HYPERBUS_TYPEDEF_HOST_W_T(__name, __data_t, __strb_t) \
+  typedef struct packed {                                      \
+    __data_t data;                                             \
+    __strb_t strb;                                             \
+    logic    last;                                             \
+  } __name;
+
+`define HYPERBUS_TYPEDEF_HOST_R_T(__name, __data_t) \
+  typedef struct packed {                            \
+    __data_t                      data;               \
+    hyperbus_pkg::hyper_resp_e   resp;               \
+    logic                         last;               \
+    logic                         atomic_ok;          \
+  } __name;
+
+`define HYPERBUS_TYPEDEF_HOST_WRSP_T(__name)       \
+  typedef struct packed {                          \
+    hyperbus_pkg::hyper_resp_e resp;               \
+    logic                      atomic_ok;          \
+  } __name;
+
+`define HYPERBUS_TYPEDEF_HOST_REQ_T(__name, __cmd_t, __w_t) \
+  typedef struct packed {                                      \
+    __cmd_t cmd;                                               \
+    logic   cmd_valid;                                         \
+    __w_t   w;                                                 \
+    logic   w_valid;                                           \
+    logic   r_ready;                                           \
+    logic   wrsp_ready;                                        \
+  } __name;
+
+`define HYPERBUS_TYPEDEF_HOST_RSP_T(__name, __r_t, __wrsp_t) \
+  typedef struct packed {                                      \
+    logic    cmd_ready;                                        \
+    logic    w_ready;                                          \
+    __r_t    r;                                                \
+    logic    r_valid;                                          \
+    __wrsp_t wrsp;                                             \
+    logic    wrsp_valid;                                       \
+  } __name;
+
+`define HYPERBUS_TYPEDEF_HOST_ALL_CT(__name, __addr_t, __data_t, __strb_t) \
+  `HYPERBUS_TYPEDEF_HOST_CMD_T(__name``_cmd_t, __addr_t)                   \
+  `HYPERBUS_TYPEDEF_HOST_W_T(__name``_w_t, __data_t, __strb_t)            \
+  `HYPERBUS_TYPEDEF_HOST_R_T(__name``_r_t, __data_t)                      \
+  `HYPERBUS_TYPEDEF_HOST_WRSP_T(__name``_wrsp_t)                          \
+  `HYPERBUS_TYPEDEF_HOST_REQ_T(__name``_req_t, __name``_cmd_t,            \
+                               __name``_w_t)                               \
+  `HYPERBUS_TYPEDEF_HOST_RSP_T(__name``_rsp_t, __name``_r_t,              \
+                               __name``_wrsp_t)
+
+`define HYPERBUS_TYPEDEF_LINK_ALL_CT(__name, __num_phys, __num_chips) \
+  typedef struct packed {                                             \
+    logic [(16*__num_phys)-1:0] data;                                 \
+    logic                       last;                                 \
+    logic [(2*__num_phys)-1:0]  strb;                                 \
+  } __name``_tx_t;                                                    \
+  typedef struct packed {                                             \
+    logic [(16*__num_phys)-1:0] data;                                 \
+    logic                       last;                                 \
+    logic                       error;                                \
+  } __name``_rx_t;                                                    \
+  typedef struct packed {                                             \
+    logic error;                                                      \
+  } __name``_wrsp_t;                                                  \
+  typedef struct packed {                                             \
+    hyperbus_pkg::hyper_tf_t trans;                                   \
+    logic [__num_chips-1:0]  cs;                                      \
+  } __name``_cmd_t;                                                   \
+  typedef struct packed {                                             \
+    __name``_cmd_t  cmd;                                              \
+    logic           cmd_valid;                                        \
+    __name``_tx_t   tx;                                               \
+    logic           tx_valid;                                         \
+    logic           rx_ready;                                         \
+    logic           wrsp_ready;                                       \
+  } __name``_req_t;                                                   \
+  typedef struct packed {                                             \
+    logic           cmd_ready;                                        \
+    logic           tx_ready;                                         \
+    __name``_rx_t   rx;                                               \
+    logic           rx_valid;                                         \
+    __name``_wrsp_t wrsp;                                             \
+    logic           wrsp_valid;                                       \
+  } __name``_rsp_t;
+
+`endif

scripts/start.tcl

@@ -15,13 +15,13 @@ proc run_test {top_name wlf_name} {
     file delete -force $transcript_name
     transcript file $transcript_name
 
-    vsim $top_name -wlf $wlf_name -t 1ps -voptargs=+acc -classdebug
+    # Questa 10.7 rejects enum assignments in common_cells clearable CDC models.
+    vsim $top_name -wlf $wlf_name -t 1ps -voptargs=+acc -classdebug -suppress 8386
 
     onfinish stop
     set StdArithNoWarnings 1
     set NumericStdNoWarnings 1
     log -r /*
-
     catch {delete wave *}
 
     run -all
@@ -37,7 +37,10 @@ proc run_test {top_name wlf_name} {
     }
 }
 
-run_test axi_hyper_tb           sim_run_axi.wlf
-run_test hyperbus_cfg_regs_tb   sim_run_cfg_regs.wlf
+run_test axi_hyper_tb_isochronous          sim_run_isochronous.wlf
+run_test axi_hyper_tb_synchronous          sim_run_synchronous.wlf
+run_test axi_hyper_tb_asynchronous         sim_run_asynchronous.wlf
+run_test axi_hyper_tb_synchronous_one_phy  sim_run_synchronous_one_phy.wlf
+run_test hyperbus_cfg_regs_tb              sim_run_cfg_regs.wlf
 
 quit -code $regression_failed -f