BSPIMX95-287 Read factory EEPROM - #16
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Show missing bits from 40-bit address. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Move address align functionality from driver into client layer so that the IEE region addess range is properly shown in the info log. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Align with M7 DDR address range as defined by SM. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Align DDR OEI and RPA supported data rates for iMX95. Signed-off-by: Michael Kjar <michael.kjar@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Local keys may not be available in some lifecycles Avoid training data sign for BLANK, FAB DEFAULT, FAB, NXP_PROV, OEM_FIELD_RETURN and NXP_FIELD_RETURN lifecycles. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v3.9.0_0.8-eff28b90a; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v3.9.0_0.8-eff28b90a; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v3.9.0_0.8-eff28b90a; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v3.9.0_0.8-eff28b90a; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v3.9.0_0.8-eff28b90a; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v3.9.0_0.8-eff28b90a; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Use "vco" and "rate" field names in fracpll_tbl explicitly for a better reading. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Refine the comments to reflect the pll rate value. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Add 5600, 2600, 2400 and 2100 data rates so that all RPA defined data rate options are covered. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Measure and save DDR OEI run time (us) in non-DEBUG mode at (QB_STATE_SAVE_ADDR - 4) offset. Later can be read in U-Boot prompt using "md" cmd. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Use memset to clean message block. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Decompose mix power up and phy reset, and start DfiClk and APBCLK beween power up and phy reset as mentioned in PHY PUB. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Update the code so that the training data signature is verified while DMA loads IMEM and DMEM FW. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Decompose ELE_VerifyData function into two non-blocking ELE_VerifyData_Tx and ELE_VerifyData_Rx functions, so that these two functions can be called independently. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Sync MIMX95_DDRC.h with SM version. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Remove "NO_OF_" from SDK PLL structure and defines so that it is aligned with recent 94 and 95 SDK versions. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Incapsulate all board init specific code into BOARD_InitHardware() function so that the board specific BOARD_InitHardware function may be modified without interfering with OEI core code. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
TCM memory following retention section is reserved by 95B0 BootROM, particularly to store temporarly V2X container. Because of this OEI stack must be be placed before retention section. Allocate for stack and BSS 0x1000 bytes, and place them right before retention section. Aligning BSS section right before stack allows additional space to be used for the OEI binary. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Avoid using TCM memory following retention section, move stack and bss sections before retention section in the same approach as in 95 linker script. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Print ELF program headers information at the end of build process. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Updated to imx-oei-LF_6.12.49_2.2.0; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Move ELF headers print under "elfinfo" rule. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
eDMA reports an error when the size is not a multiple of the src/dst transfer size in the TCD ATTR reg. Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
Move the qb data saving location from NPU SRAM to DRAM. Introduce mandatory CRC32 to ensure data integrity. Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
Timing file having enabled only channel A. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_3.6-c460ca712; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_3.8-c460ca712; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_0.4-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_0.4-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_0.3-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_0.3-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_1.2-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_1.1-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.0.0_1.1-ac07e4ce6; Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_1.3-bbe174500. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_1.2-bbe174500. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_1.2-bbe174500. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_0.5-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_0.5-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_0.4-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_0.4-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_3.9-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_3.7-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Blank sync timing update to DDR Tool v4.1.0_3.7-4041521b6. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Update SBOM for RC2 code freeze. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Add details regarding the expected toolchain location, location format and methods to change default toolchain version. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
SoC revision shown in OEI output displays $(REV) compilation parameter value and not the real SoC revision. Refine the DDR OEI output in order to avoid confusion. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Merge conflict in oei/makefiles/gcc_cross.mak Signed-off-by: Yannic Moog <y.moog@phytec.de>
Follow suit with commit 86f1ab0 ("boards: incapsulate all board init specific code into BOARD_InitHardware"), which removed the hardware init functions from main and expects each board to define its own code. This resolves a link error where BOARD_InitHardware was undefined for mx95libra. Signed-off-by: Yannic Moog <y.moog@phytec.de>
Add an option to differentiate between enabling a debug console and enabling additional debug messaging. This commit introduces logging via debug console by default and additional messages can/will be printed when the DEBUG option is enabled as well. When DEBUG is set to 1, CONSOLE will also be enabled Signed-off-by: Yannic Moog <y.moog@phytec.de>
In preparation of reading data from an I2C EEPROM on PHYTEC boards, add an lpi2c driver for the i.MX 95. The driver is a copy of the driver found in the imx-sm project. Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
basic skeleton for init and read function. WIP Signed-off-by: Yannic Moog <y.moog@phytec.de>
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The goal of this PR is to introduce support to read factory EEPROMs on PHYTEC SoMs (and print the contents in human readable format).
This is a first step for initializing main memory with appropriate timing values depending on which capacity is populated on the SoM.
No driver support is present for i2c devices (neither host nor device). Implement/add drivers first and then add SoM detection code.
Depends on 2026q2 release as that introduces the possibility of adding board code easily.